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aes implementation on fpga

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jhunjhun

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i have seen the code but there is no way to use 2D array. Please reply soon
very thankfull 2 u....
 

jhunjhun said:
i have seen the code but there is no way to use 2D array. Please reply soon
very thankfull 2 u....
Click to expand...

Instead of a 2D Arrray ,you can opt for a look up table ...if verilog

VHDL supports 2d array
 

how to use look up table................can you help me ??

- - - Updated - - -

how to use look up table................can you help me ??
 

First of all Read this
h**p://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
In order to create an Sbox you can go for a look up table
 

i have read this
h**p://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
how to create look up table?please suggest me..........
 

You need to study any one of those HDL like Verilog or VHDL
h**p://www.verilogtutorial.info/
 

can you please suggest me ??how to implement aes on fpga step by step???
 

thanks vipinlal but i could not download it. pls tell me how to open that document.
 

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