Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

INOUT and BUFFER in VHDL

Status
Not open for further replies.
B

Bustigo

Member level 2
Member level 2
Joined
May 7, 2011
Messages
53
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,588
i never used inout and buffer in vhdl
but i dunn know when to use them and what is the differences between and what is them :D ??
 

inout - is used for ports that can both be an output and an input. They're called tri state buffers
if you define a port as inout, you also have to define it's behaviour.
Suppose "some_inout " is defined as an inout std_logic port in your entity.
Code: 
some_inout <= x when control_signal = '1' else 'Z' ;
when "control_signal" is '1' "some_inout" functions as an output.
when "control_signal" is '0' "some_inout" functions as an input.

To understand the buffer type you have to know about a strange limitation that VHDL has...a simple "out" port cannot be read back to the design(!).
Suppose "some_out" is a port that defined as an "out" std_logic in your entity. you won't be able to read back the value of "some_out" in the same architecture:
For example, you won't be able to write:
Code: 
if some_out = x then
-- do something --
end if ;
You'll have to define and use an intermediate signal like this:
Code: 
some_out <= intermediate_some_out;
if intermediate_some_out = x then
-- do something --
end if ;
A buffer type is an output type that unlike a simple "out" - can be read back without problem...so you can write:
Code: 
if intermediate_some_out = x then
-- do something --
end if ;

- - - Updated - - -

You can also read this:
http://vhdlguru.blogspot.co.il/2011/02/how-to-stop-using-buffer-ports-in-vhdl.html
I'll note that the use of buffer type is discoraged by many...
Myself, I'm not convinced.
 
Last edited:
Bustigo said:
i never used inout and buffer in vhdl
but i dunn know when to use them and what is the differences between and what is them :D ??
Click to expand...
- inout is used when there are multiple drivers for a signal (like in a model of a bus on a printed circuit board. For example, the data bus connecting a processor to some external memory). When describing the logic that is inside a programmable part such as an FPGA, there is no real use for 'inout'.
- buffer is used when there is only one driver, the signal is also referenced in the entity that drives that signal and you're compiling with a tool that does not support VHDL-2008.

Kevin Jennings
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top