INOUT and BUFFER in VHDL

i never used inout and buffer in vhdl
but i dunn know when to use them and what is the differences between and what is them ??

inout - is used for ports that can both be an output and an input. They're called tri state buffers
if you define a port as inout, you also have to define it's behaviour.
Suppose "some_inout " is defined as an inout std_logic port in your entity.
when "control_signal" is '1' "some_inout" functions as an output.
when "control_signal" is '0' "some_inout" functions as an input.

To understand the buffer type you have to know about a strange limitation that VHDL has...a simple "out" port cannot be read back to the design(!).
Suppose "some_out" is a port that defined as an "out" std_logic in your entity. you won't be able to read back the value of "some_out" in the same architecture:
For example, you won't be able to write:
You'll have to define and use an intermediate signal like this:
A buffer type is an output type that unlike a simple "out" - can be read back without problem...so you can write:

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You can also read this:
http://vhdlguru.blogspot.co.il/2011/02/how-to-stop-using-buffer-ports-in-vhdl.html
I'll note that the use of buffer type is discoraged by many...
Myself, I'm not convinced.

Bustigo said:

i never used inout and buffer in vhdl
but i dunn know when to use them and what is the differences between and what is them ??

Click to expand...

- inout is used when there are multiple drivers for a signal (like in a model of a bus on a printed circuit board. For example, the data bus connecting a processor to some external memory). When describing the logic that is inside a programmable part such as an FPGA, there is no real use for 'inout'.
- buffer is used when there is only one driver, the signal is also referenced in the entity that drives that signal and you're compiling with a tool that does not support VHDL-2008.

Kevin Jennings

Thank You for your replies