Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

path exercised by test bench vectors in a gate-level or RTL design

Status
Not open for further replies.
T

tariq786

Advanced Member level 2
Advanced Member level 2
Joined
Feb 24, 2004
Messages
562
Helped
67
Reputation
134
Reaction score
54
Trophy points
1,308
Location
USA
Activity points
3,050
Hi guys,


if i run test bench vectors through a design, how can i see and list all the paths exercised by the input vectors in a gate-level design or RTL design?
 

any one ???

Its strange that no body replied.
 

Hi i think you need the coverage report which will throw throw light on the paths being unsensitized.
 
there should be other ways to get this information besides coverage report. Who can help me with that?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top