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Relationship between core consumption and frequency

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shaiko

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Should changes in the operating frequency of an FPGA/CPLD cause changes in the current consumption of the Core ?
 

Dear shaiko
Hi
This formula is for all kind of digital systems :
(Vcc^2)*C*F+VCC^2/2RL if you increase the VCC , you'll see the consumption will increase .
Best Wishes
Goldsmith
 
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    shaiko

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Thanks goldsmith,

But I was asking about the FPGA's core current conssumption...
 

This formula is for power consumption . thus you have the power , and of course operation voltage , with a simple division you can obtain current consumption .
 

The above may be good for small discrete devices.
However, it's useless for the current consumption calculation/estimation of HUGE SYSTEM like an FPGA core.
 

I have no idea about it , because my interest isn't in digital systems . but as i can remember , one years ago , i saw a video from MIT university . in that the professor , calculated power consumption of a pentium 4 CPU . he considered that it has at least 10^8 digital gates ( he told it is not for pentium four , because it has 20 million digital gates . ) but it was an example .
I hope this description can help you . and sorry if i can't help you as well because my field is analog .
Good luck
Goldsmith
 
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    shaiko

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What do you mean by FPGA "core" specifically? The entire chip?

If the whole FPGA is running from one clock, it should obey the standard rules for power consumption - it's made from millions of discrete logic elements, and on average they will all follow the same rule.

If your FPGA is using multiple clocks of different frequencies, you will need to consider the amount of logic running at each frequency. Your FPGA vendor should provide you with power estimation tools.
 

Generally, an FPGA has a voltage that must be supplied it's "core" - usually it's something in the range of 1.2V (technology dependent)
"core" is how the manufacturers call it...not just me.

My question:
Will current consumption to this section of the FPGA rise when clock frequency rises ?
 

I think the current consumption will increase. More freq means the flip flops in the fpga switch more often per sec. Which means the average current drawn by the circuit will be more. This is what I think.

But if its only a combinational circuit then, freq shouldnt change any current consumption.
 

If the clock is driving internal logic, then this is powered by the 'core' voltage. So the answer to your question is yes. Why would you think it would not?

If the clock is driving I/O buffers, these may be powered at different voltages (e.g. 3.3V) and you'll need to consider this if calculating power usage. You might run your I/O at a different speed to most of your internal logic, of course.
 

I think the current consumption will increase. More freq means the flip flops in the fpga switch more often per sec. Which means the average current drawn by the circuit will be more. This is what I think.
Click to expand...

vipinal,
I agree with every word. However, testing revealed a different reality.

If the clock is driving internal logic, then this is powered by the 'core' voltage. So the answer to your question is yes. Why would you think it would not?
Click to expand...
joelby,
As I replied to vipinlal - I actually thought it would...

However, After increasing the clock frequency driving an Actel Igloo FPGA from around 32KHz to a 50MHz - I saw absolutely zero change (not even a single microamp) in current to the core.
Just to note - the design that was tested wasn't purely combinatorial - it had around 1K of operational flip flops in use.

Weird indeed.
 

That seems odd. If the answer isn't clear from reading the Igloo data sheet or by fiddling with its power calculator, it would be worth contacting Actel support directly.
 

when you tested, did the analysis showed any change in the power?

can u paste the analysis results here..
 

vipinlal,
I've no change in current consumption to the core when I increased the frequency...
 

No analysis has been made.
I did a true empirical test...measured the current consumption of the core with a high percision ammeter while driving the clock with an external signal generator.
The results showed no correlation between clock frequency and core current consumption
 

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