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EDIF file is vendor-neutral PnR netlist file, which is generated by synthesis tools (like Synplify pro) and contains all information about connections of different FPGA resources to implement the wanted logic. Place & roue tools take this file in addition to physical constraints file (containing information about IO pins & timing constraints) and does place & route. Information at following link will further clarify your doubts: https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_xst_for_synthesis.htm.
EDIF file itself contains information about resources as well as their connections (simply whatever you see in technology view) after synthesis. Definition of exact resources available in a particular FPGA is provided through component libraries in the synthesis tool.
Yes.. to some extent but that may be specific to a particular FPGA, because though the format of EDIF file is vendor independent but synthesis tool uses component libraries of that FPGA to create it.
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