Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Difference between constant and unloaded flip-flops?

Status
Not open for further replies.
E

er.akhilkumar

Full Member level 2
Full Member level 2
Joined
Feb 1, 2011
Messages
123
Helped
4
Reputation
8
Reaction score
4
Trophy points
1,298
Location
Noida
Activity points
2,443
Hello All,

Can anyone please tell me that what is the difference between constant and unloaded flip-flops?

Actually I have seen it in the following command of dc_shell:

Step 14. Set Register optimization veriables (optional)
(a) Set automatic removal of constant flipflop(s)
set compile_seqmap_propagate_constants true
(b) Set automatic removal of unloaded flipflop(s)
set compile_delete_unloaded_sequential_cells false

Source: http://www.vlsiip.com/dc_shell/

Thanx
 

This is an optimization strategy calleD Sequential mapping. Go through the chapter nine(9) of dcug. you will get all your answers if you still have any questions regarding that post here..

Cheers.
 

a) FFs without input signal or clock
b) FFs without output connection
Both are useless in a design.
 

Actually while doing synthesis I am getting one notification due to which I am having mapping problems in LEC. It shows "flip_flop output name_reg is constant and will be removed". What is meaning of this line?

- - - Updated - - -

Actually while doing synthesis I am getting one notification due to which I am having mapping problems in LEC. It shows "flip_flop output name_reg is constant and will be removed". What is meaning of this line?

- - - Updated - - -

@vijay.mani884: What is dcug?
 

I think, it's only indicating a problem, if you expect the removed signal to carry an essential information in your design.
 

@ FvM You are right. I think ppl need to think first than ask ;)
 

often, FF's will be removed for being constant. one example is a counter that is reset to 0, then incremented by 2 (or 4, 6, etc...). There is no way to get an odd result, so the build tools will realise the lsb is a constant 0. This can then propagate down to other logic, eg comparisons to odd values will be false and comparisons to even values can be done with 1 fewer bit.

For unconnected logic, consider a 32b counter where the only comparisons are to bits 23:8. The 8 lsbs (7:0) would need to be kept because they are used to generate bit 8 (and higher). but the 8 msbs (31:24) aren't used for anything other then generating themselves. They are still connected to each other, and logically valid for simulation purposes, but their removal will not affect the comparison of bits 23:8. As a result the tools may just remove the 8 msbs.
 
  • Like
Reactions: erikl

    erikl

    erikl

    Points: 2
    Helpful Answer Positive Rating
@permute: I have written code for a combination logical which contains FOR loop. So shall I stop the tool from optimizing this code? Or is there any other way to do this as I am unable to detect the problem in code?
 

Hi,

As you are getting problem in LEC, one way to proceed, is to prevent the FLOP form getting optimized. You can set the attribute "dont_touch" true on that Flop, this will
prevent that flop from getting optimized.

hope this helps,
Shobhit
 

But Shobhit, I want to know the problem why it is removed by tool. It could also happen that I have designed some false path. So please tell me the way to track that problem.
 

Hi akhil,

Some constant might be propagating up to the flop which is causing the optimization of the flop.
The things you can do-->
1. Do check the log for the warnings, you must be getting the warning related to that flop being removed and also the reason of removal.
2. Before the tool optimizes, save the database, and check for the case values being propagated up to the flop
3. The logic may be such that, the particular flop may be becoming redundant, which could cause its removal.
4. The flop may be unloaded, in that case also the flop may be removed.

thanks,
Shobhit
 
Thanx for your reply Shobhit, can you tell me what is the meaning of unloaded flip-flops?

Thanx
 

Unloaded = not connected to a load = not driving other logic
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top