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Mixed VHDL and Verilog design

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shaiko

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I'm stepping into a project that involves mixed language design (VHDL and Verilog).
Most of the files are *.V while some are *.VHD
How do I compile them to a single project ?
 

This is called "instantiation by position" right ?
 

yes... but the concept applies for both instantiation by position and by name..
 
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    shaiko

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the concept applies for both instantiation by position and by name
Click to expand...

Suppose I have a verilog file named : "some_verilog_file.v" and in this file there's a module named: "some_verilog_module".

If I want to instantiate this module in a different VHD file - all I need to do is declare "some_module" as a component and instantiate it - as if "some_module" was a true VHDL written entity ?
 

yes... thats what is done is that example..
 
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    shaiko

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Yes it is done this way.

Make component for your verilog code and simly instantiate it like

https://www.xilinx.com/itp/xilinx10/isehelp/ism_p_instantiating_verilog_module_mixedlang.htm

Code: 
--VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity vhdl_top is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : out  STD_LOGIC);
end vhdl_top;

architecture Behavioral of vhdl_top is

component ver_cnt is 
port(
a: in std_logic;
b: in std_logic;
c: out std_logic
);
end component;

begin

--instantiation
uut : ver_cnt port map(a => A, b => B, c => C);

end Behavioral;

Code: 
//Verilog Code
module ver_cnt(
    input a,
    input b,
    output c
    );

assign c= a ^ b;

endmodule
 

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