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error in vhdl (is controlled by a clock but does not appear to be a valid sequential)

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Hello.
I have a problem with this program . this program are complied correcty in modelsim without any error,but when I use ISE ,I face with this error?
how can I resolve this error?
who can help me?
the error:
Logic for signal <i> is controlled by a clock but does not appear to be a valid sequential description.

Code: 
process(clk,reset,clk_external)
    variable  i,s,a,c :int:=0;
    begin 
      if reset ='1' then 
        s:=0;i:=0;multiple_sign:=1;
      else
        if (clk 'event and clk='1' )then
          if (clk_external 'event and clk_external='1' ) then
           i:=1;s:=0;--multiple_sign:=1;
          else
           i:=i+1;
          end if;
        end if;
 

You can't nest edge sensitive events for synthesizable VHDL. The edge sensitive evaluation of a signal represents a FF in hardware, each FF can have only one clock input, so for each signal assigned in a clocked process, there must be one and only one edge sensitive statement.

As an additional remark, although the code seems to compile in Modelsim, it most likely won't work. The nested condition will be only true, if both clock edges fall in the same simulation delta cycle.

P.S.:
how can I resolve this error?
Click to expand...
As a first step try to describe the intended behaviour in regard to both clocks, e.g. in a timing diagram. How they are related?
 
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