set clock latency issues

Hi,
can anyone pls explain how should i use this command?
should i set the latency on the clock port?
does it affect the early or late path?
if i have gated clocks in my design, i must use also set_clock_gate_latency?

Thanks!

You forgot to post the command....

i meant set_clock_latency command...

If you want some help I must help us to help you.
Good luck.


+++

ee1 said:

Hi,
can anyone pls explain how should i use this command?

Click to expand...

set_clock_latency command is used to define the estimated clock
insertion delay during synthesis. This is primarily used during the pre-
layout synthesis and timing analysis. The estimated delay number is an
approximation of the delay produced by the clock tree network insertion
(done during the layout phase).

ee1 said:

Hi,
should i set the latency on the clock port?

Click to expand...

yes.

ee1 said:

Hi,
does it affect the early or late path?

Click to expand...

both. you can look at the setup and hold time report in PrimeTime.

Thanks.

hi,
Latency wont affect late/early paths. Uncertainty will affect. latency is used to model two things.

1. Source Latency i.e "from PLL to the Clock definition point in your design"
2. Network Latency i.e "From the clock definition point to the flop clk pin"

Usually, Souce latency wont change for the design as it is taken from the PLL specifications. as far as network latency is concerned the Tool "PT" will calculate it for you.

Cheers

hi vijay,
how uncertainity will affect timing late/early paths?
uncertainity = skew+jitter,
latency is reason for the skew.then how we can say that latency w't affect.?

Nope, latency is not the reason for the skew. Kindly check once. Latency is teh time taken by a clock signal to propagate from its definition point to the flop/clock pin (i am assuming network latency). This is a clear cut delay. thus called insertion delay. You can find any changes in the width of the clock waveform. Where as uncertainty is a factor that models "skew+jitter+otherpessimismvalue" now the question is what is this other pessimism value? This is youe derating factors which is done on the early and late paths.

So, never confuse on these two terms dude. Remember, Latency is related to time it takes to propagate through the path. But uncertaininty is the factor which we add to tighten up the margins.

Say for example if we specify
set_clock_uncertainty -setup 0.2 [get_clocks my_clk]
set_clock_uncertainty -hold 0.05 [get_clocks my_clk]

what will it do? It will reduce the setup margin by the amount specified but add the hold margin by the amount specified. Now compare what will a latency do.

Cheers

thank u.. i got clear idea about uncertainity....and another one doubt
i saw one document
if consider reg to reg path data arrival time =clocklatency+cell/netdelay
data setuprequired time=clockperiod+clocklatency-clockuncertanity-outputdelay.
data hold reqired time=clocklatency+clockuncertanity-outputdelay.
can u explain this ple...bcoz here they putting latency...