msp4u4ever
Newbie level 5
Hello all,
I have a system implemented in two different ways (using verilog).
How can I compare the hardware complexity of both the designs?
Is it possible to compare the hardware complexity by synthesizing both the designs using a single cell (2-input NAND gate etc)?This way we will know the total gate count of both the designs?
How can we do that in Synopsys Design Compiler?
If this is not the way, how do we compare the hardware complexity?
I have a system implemented in two different ways (using verilog).
How can I compare the hardware complexity of both the designs?
Is it possible to compare the hardware complexity by synthesizing both the designs using a single cell (2-input NAND gate etc)?This way we will know the total gate count of both the designs?
How can we do that in Synopsys Design Compiler?
If this is not the way, how do we compare the hardware complexity?