The difference between simulation and synthesis

simulation and synthesis

what's diffenerce there are between Simulation and synthesis?

simulation and synthesis

They have different objects. The Simulation can verify the timing of the circuit. The synthesis can output the netlist.

simulation and synthesis

From SW designers' view, Simulation process is sth like the debugging process, while the Synthesis process is sth like the compile-link-make process. what's more, the Synthesis process is the key point of EDA technology, which makes the Automatic process possible, and also interesting...

Re: simulation and synthesis

Simulation is verifying the functionality of the design and synthesis is the implementation of the design in to the actual hardware.

Re: simulation and synthesis

Simulation comes after synthesis. Design must synthesize first prior to simulation.

simulation and synthesis

Hello
The difference between simulation and synthesis is simple
Simulation is nothing but what ever expected logical functionality checking in Hardware world,
with out considering the actual timing issues i.e net delays and ckt delays

where as synthesis is actually targetting your functionally rather logically verified design to the proplerly targetted technology like 90nm technology etc
After synthesis you can check that whatever funtionality you are expecting is achived with repect to all the reality deviced place

need more clarification you can contact me

Re: simulation and synthesis

SYNTHESIS is related to ur Target devive architecture.
SIMULATION is just verification of ur logical design

Thanks
USMAN HAI

Re: simulation and synthesis

delay said:

Simulation comes after synthesis. Design must synthesize first prior to simulation.

Click to expand...

Not really. Depend of what king of simulation are you talking about

Re: simulation and synthesis

In a few words:
Simulation is to verify that the design would work as we intended
synthesis is to translate the design into a next level of abstraction.
for examle from RTL level to gate level

Re: simulation and synthesis

Simulation is to verify your design. Thus it is first step after your design and coding is done. It is totally software activity where you verify your design using simulators like ModelSim. This step is also called as functional simulation.
Once you have verified your design, you need to target your design into hardware. So you need to convert your RTL into gate level design. Synthesis is divided into three steps: Translation, Optimization and Technology Mapping.
Translation: RTL to gate-level netlists.
Optimization: technology-independent logic-level optimization to reduce hardware for required functionality.
Technology Mapping: technology-independent netlists are transformed into technology-dependent ones.
Synthesis tools do all these steps. Designer needs to specify the optimization constraints, which the synthesis tool tries to meet.
After synthesis there is one more simulation called Timing simulation.
It may appear difficult for the first time but you will understand it as you study more about it. You may not be familiar with some of the terms, feel free to ask any doubts.
Regards,
Jitendra.

simulation and synthesis

synthesis is to transfer the RTL code to gate level .
simulation is to verify the RTL or gate level function.

Re: simulation and synthesis

hi folks

the difference between simulationa and synthesys is that in simulation we r able to check the expected output at a given time for which we write a rtl code while synthesys means the realization of the rtl code in the physical circuit made from the standard libraries availble.

ashish

Re: simulation and synthesis

Salam ALL,

delay wrote,

Simulation comes after synthesis. Design must synthesize first prior to simulation.

Click to expand...

In fact, There are two kinds of simulation

1- behavioral (functional) simulation which is done pre-fit (before synthesis)
2- Timing simualtion which is done post-fit (after synthesis) to ensure that it has achived the required timing.

Synthesis is process of convert RTL HDL design to Gate level netlist, Then optimize and map this netlist according to the vendor technolgy.

Bye
SphinX

Re: simulation and synthesis

I didn't mean to mislead here.

A lot of literature refers to functional simulation without synthesizing the code. However, this may be a good way for an experience designer who has simulated similar modules in previous designs. It may not be necessarliy wise to spend time on functional simulation prior to synthesis because after all if the initial synthesized circuit is poor on area or speed, then several portions of the code will be rewritten even though the design is functionally correct. Therefore early post-synthesis is advisable to see what are the expected results.