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It depends...if the 'if' statement specifies mutually exclusive conditions that could have been implemented with a case statement, then there is no difference.What would be infered in the fpga for case statement and if statement?
My previous answer still appliesOh, sorry. What I was assuming was that there is a cascaded if statements such as if...elsif....elsif....
"case" statement will inferr a mux logic in fpga. where, "if" statement will infer a rpiority encoder?
My previous answer still applies
Hm... Really? As far as I know, the implementation from case and if statements were different. I don't know how the synthesizer can create case statement from multiple if-elsif statement. I thought that was the reason designers prefer using case statement instead of if... is it not?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 signal a : integer range 0 to 3; case a is when 0 => --do something when 1 => --do something else when 2 => --do a third thing when 3 => --make some toast end case; if a = 0 then --do something elsif a = 1 then --do something else elsif a = 2 then --do a third thing else --make some toast end if;
Code VHDL - [expand] 1 2 3 4 5 if cond1 then --do something elsif cond2 then --do something else end if;
And what 'you know' is based on synthesizing a circuit or just guessing? It appears to be guessing.Hm... Really? As far as I know, the implementation from case and if statements were different.
Perhaps you should read what I wrote in my first post. If the conditions in the 'if' statement are mutually exclusive as they would have to be in order to be able to use a 'case' statement instead, then the synthesizer will create the same logic.I don't know how the synthesizer can create case statement from multiple if-elsif statement.
Designer preferences are not the topic though are they?I thought that was the reason designers prefer using case statement instead of if... is it not?
And what 'you know' is based on synthesizing a circuit or just guessing? It appears to be guessing.
I thought you said that your answer still applies, didn't you?Perhaps you should read what I wrote in my first post. If the conditions in the 'if' statement are mutually exclusive as they would have to be in order to be able to use a 'case' statement instead, then the synthesizer will create the same logic.
Perhaps YOU should read what I wrote. I did not say that designers "prefer" using case statement for no reason. I said that they use it because of the reason I explained.Designer preferences are not the topic though are they?
I may, when I get a chance.Perhaps you and the OP should construct a test case and synthesize it both ways to prove to yourself.
if a = 1 then
if b = 2 and c = 3 then
en_1 <= '1';
if d = 40 and e = 50
en <= '1';
else
en <= '0';
end if;
en_1 <= '0';
end if;
end if;
The example you posted can't be expressed as a case statement at all which renders the comparison between 'if' and 'case' moot. The person writing this code could not choose between using 'if' and 'case' any more than they would choose between 'if' and 'with/select'.Well, there are certain limitations(Maybe hesitation) in using if and case statements in all situations. You cannot use a case statement very well for a nested-if statement. For eg.
Code:if a = 1 then if b = 2 and c = 3 then en_1 <= '1'; if d = 40 and e = 50 en <= '1'; else en <= '0'; end if; en_1 <= '0'; end if; end if;
Similarly for describing a state machine, case statements are best at it's own. So it is purely based on the designer point of view. Because both has it's own pros and cons.