[SOLVED] vhdl code : help regarding port mapping

hi...
i ve written certain modules in vhdl;
Now i ve to SELECT THE MODULES(components) for operations BASED ON SOME CODITIONS.

1. But i learnt port mapping cant be done for conditions... (port mapping cant be done inside process)
2. are there any concurrent conditional' port mapping statements'
3. OR ANY WAY ROUND.

regards,

Think about what you're asking. Imagine an entity is like a chip on a circuit board. You cant just conditionally add a chip while the circuit is running.

You have to use control signals to control the dataflow, not instantitate as and when its needed.

So the answers are:
1. No for runtime, but you can use generics and generate statements that conditionally create logic at compile time.
2. Not for runtime
3. No

thanks,

what about the implications on field(board)......?

I ve been implementing the design in mixed style; STRUCTURAL and BEHAVIORAL styles.
For the points u made;

I inferred that during runtime; i will be getting the outputs from all modules , but i shall select my needed data as on conditions.

"""""""On board too, the computations will be done for all modules and later selected????????"""""""





I REALLY APPRECIATE YOU FOR BEING SO CONSIDERATE THE REPLY IS SO HELPFUL

As Tricky said, port map, configurations, generate, generic all these in VHDL help user design a piece of code which can comply for many needs. For example, a user may design a small VHDL design with 32-bit interface, and the other user may want to use 64-bit. If your code uses these types for all definitions, your code can very easily be upgraded for 64-bit with ease. If not, you need to work out more.

On field, these will not account into. For example, you cannot pass generic values in real time, the same for configurations too....These are so handy in simulation and compilations only

---------- Post added at 15:35 ---------- Previous post was at 15:25 ----------

vjkr said:

I inferred that during runtime; i will be getting the outputs from all modules , but i shall select my needed data as on conditions.

"""""""On board too, the computations will be done for all modules and later selected????????"""""""

Click to expand...

Well, it would be no.
Either you can use gated clocks to enable\disable clocks to certain parts of logic, as you like (for Power save\interference), but not with these generate\configurations dude.

Thanks a ton, TrickyDicky;xtcx.