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[SOLVED] Problems with DesignCompiler/PrimeTime Flow

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hbeck

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Hello everyone,

I did a synthesis of my design with the Design Compiler and Formality signals me that all compare points are equal (*.ddc vs. RTL). Also its possible to read back the ddc file with DesignVision and generate some schematics. But when I read my design into Primetime by typing:

Code: 
read_ddc xxx.ddc
link_design

The output shows that almost every submodule is skipped, due to unresolved reference:

Code: 
Warning: Unable to resolve reference to 'xxx' in 'xxx_top'. (LNK-005)
Creating black box for i_xxx/xxx...

How can that happen? The technology setup (search_path / link_library) is the same as used for synthesis and logic equivalence check. I did that with local .synopsys_dc.setup and .synopsys_pt.setup files.

Any hints? Thanks in advance.

(Versions: DC F-2011.09-SP4, PT F-2011.12-SP3)
 

can you try this...
in DC
dc_shell-t> list_libs
and in Primetime

pt_shell> list_libraries


it will tell you the libraries and in both the cases. See if there paths are same.
 
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    hbeck

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I suppose you netlsit must have some generic (**GEN** cells in the write out netlist) cells in at synthesis, which are not mapped at synthesis.
You can re-synthesis your design, and write out a *.v along with *.ddc. Then search "GEN" in the write out *.v.
Thanks.
 
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birdy123 said:
can you try this...
in DC
dc_shell-t> list_libs
and in Primetime

pt_shell> list_libraries


it will tell you the libraries and in both the cases. See if there paths are same.
Click to expand...

DC tells me:

Code: 
Logical Libraries:
-------------------------------------------------------------------------
Library		File			Path
-------		----			----
  tcbn90ghpwc_ccs tcbn90ghpwc_ccs.db	/tcbn90ghp_210b/TSMCHOME/digital/Front_End/timing_power_noise/CCS/tcbn90ghp_210b
  dw_foundation.sldb dw_foundation.sldb	/usr/synopsys/syn_vF-2011.09-SP4/libraries/syn
  gtech		gtech.db		/usr/synopsys/syn_vF-2011.09-SP4/libraries/syn
  standard.sldb	standard.sldb		/usr/synopsys/syn_vF-2011.09-SP4/libraries/syn

And now PT:

Code: 
Library Registry:
 *  tcbn90ghpwc_ccs   /tcbn90ghp_210b/TSMCHOME/digital/Front_End/timing_power_noise/CCS/tcbn90ghp_210b/tcbn90ghpwc_ccs.db:tcbn90ghpwc_ccs

The only difference are the generic libs at DC. But netlist should not contain anything out of them?!

yx.yang said:
I suppose you netlsit must have some generic (**GEN** cells in the write out netlist) cells in at synthesis, which are not mapped at synthesis.
You can re-synthesis your design, and write out a *.v along with *.ddc. Then search "GEN" in the write out *.v.
Thanks.
Click to expand...

The netlist doesnt contain any "GEN". Hierarchy is still available, therefore every submodule has an own "module xyz [...] endmodule". I double checked that all modules which are not found by PT are available.

:???:
 

Peharps, DC command write -f ddc ... doesn't contain option -hierarchy.
 
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Ya that may be problem (as mention by poluekt).

try one more thing- load the complete netlist in PT and then use the current_design $sub_module command.

so its like if ur submodule is "abc" which is failing...

then do
> current_design ABC
> link

now see whether you are able to link the design ABC. If you are not able to link this sub_module - check the reason .. may be some library does not found.

let me know in case it helps you.
 
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    hbeck

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birdy123 said:
Ya that may be problem (as mention by poluekt).

try one more thing- load the complete netlist in PT and then use the current_design $sub_module command.

so its like if ur submodule is "abc" which is failing...

then do
> current_design ABC
> link

now see whether you are able to link the design ABC. If you are not able to link this sub_module - check the reason .. may be some library does not found.

let me know in case it helps you.
Click to expand...

Now it gets weird. I did what you advise me:

Code: 
read_ddc -netlist toplevel.ddc
current_design toplevel
link_design
 -> Loading db file '/TSMCHOME/digital/Front_End/timing_power_noise/CCS/tcbn90ghp_210b/tcbn90ghpwc_ccs.db'
 -> Linking design toplevel...
 -> Warning: Unable to resolve reference to 'x1' in 'toplevel'. (LNK-005)
 -> Warning: Unable to resolve reference to 'x2' in 'toplevel'. (LNK-005)
 -> Creating black box for i_x1/x1...
 -> Creating black box for i_x2/x2...
...

remove_design -all

read_ddc -netlist toplevel.ddc
current_design x1
link_design
 -> Warning: Module 'x2' in file 'toplevel.ddc' is not used in the current design .  (LNK-039)
 -> Warning: Module 'x3' in file 'toplevel.ddc' is not used in the current design .  (LNK-039)
 -> ...
 -> Design 'x1' was successfully linked.

After that I got the schematics of x1 without any blackboxes. :shock: I dont get the problem.

(hierarchy option for DC ddc output was set correctly)

---------- Post added at 16:58 ---------- Previous post was at 15:50 ----------

I got it! :cool:

Design Compiler uses link_library, PrimeTime uses link_path instead! I used the same setup as for DC and therefore no link_path ...
 

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