synthesis in Design Compiler

Hi..

I have implemented my VHDL code and want to synthesis it on DC (design compiler). but my synthesis is very slow and at last it gives fatal error at last.
can anybody knows what is problem and where am going wrong?

please show us what's the fatal error.

fishinger said:

please show us what's the fatal error.

Click to expand...

The tool has just encountered a fatal error:

If you encountered this fatal error when using the most recent
Synopsys release, submit this stack trace and a test case that
reproduces the problem to the Synopsys Support Center by using
Enter A Call at https://solvnet.synopsys.com/EnterACall.

* For information about the latest software releases, go to the Synopsys
SolvNet Release Library at https://solvnet.synopsys.com/ReleaseLibrary.

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Release = 'C-2009.06-SP5-2' Architecture = 'linux' Program = 'dc_shell'
Exec = '/usr/synopsys/syn/linux/syn/bin/common_shell_exec'

'238185756 238187626 238307291 238542061 172428785 172479516 172513889 172522170 172567778 156887509 156888318 157289123 156367648 156379466 156391821 152747740 151698940 237927711 239745242 239751322 239910386 239931765 239755351 239957361 237920125 145060165 145042397 145771640 145731789 145738302 145717663 140700009 135926695 135923893 245122662 135951215 135948767 248755537 246430865 243927577 243936624 243937227 241111588 243932639 244614050 240777132 240798309 144795337 248669419 240787062 241212014 241207254 241351382 139093347 248674649 139092947 240055933 139093682 248665789 248666189 245120954 146205605 146207269 135925048 135925373 135948565 248755537 240749377 240752079 244552747 244561652 241111588 244542725 240777132 240798309 144795337 248669419 240787062 241212550 241207254 241351382 139093347 248674649 139092947 240055933 139093421 248665789 248666189 248674221 240775335 144737202 144726931 148301717 134623195 134609050 9280470'

1: dc_shell-t -64
2: use server with more physical memory.

I don't advice to use 64-bit version.
Try command:
compile -incremental

poluekt said:

I don't advice to use 64-bit version.
Try command:
compile -incremental

Click to expand...

me tried that also but in that same fatal error.

Are you using a script for compiling or you manually implement it on Design Vision? In fact, some sophisticated designs can run faster 2-3 times if you're using scripts.

Fatal errors occur when you have some strong problem in design. Actually it could be anything: area or time violations, wrong op conditions and so on. If all steps before "compile" have no issue, try to change compile strategy: start with launching without any constraints, and if it's good, add constraints gradually.

I wonder, is there any way to make DC give full response about fatal error, without this useless information about support.

Hello,

First of all try and give the memory option for the tool. Check with your senior for the command for allocating memory, may be your design is not getting the sufficient memory for performing the synthesis.

Cheers.

vijay.mani884, which memory options has DC? I know that exist multithreading options (set_host_options -max_cores, compile -num_cores), but in modern versions DC this feature executes automatically.

Fatal errors occur when you have some strong problem in design. Actually it could be anything: area or time violations, wrong op conditions and so on. If all steps before "compile" have no issue, try to change compile strategy: start with launching without any constraints, and if it's good, add constraints gradually.

Click to expand...

Yes, I too had such issue with set_max_leakage_power, set_max_area constraints.

poluekt said:

vijay.mani884, which memory options has DC? I know that exist multithreading options (set_host_options -max_cores, compile -num_cores), but in modern versions DC this feature executes automatically.

Yes, I too had such issue with set_max_leakage_power, set_max_area constraints.

Click to expand...

I am talking about, increasing the server physical memory. I dont remember the command though, For my case, it solved the problem. check with your senior, he would be knowing it.

yx.yang said:

1: dc_shell-t -64
2: use server with more physical memory.

Click to expand...

i tried dc_shell-t -64 but same error.

How to give more memory to server?

---------- Post added at 19:51 ---------- Previous post was at 19:49 ----------

kopern1k said:

Are you using a script for compiling or you manually implement it on Design Vision? In fact, some sophisticated designs can run faster 2-3 times if you're using scripts.

Fatal errors occur when you have some strong problem in design. Actually it could be anything: area or time violations, wrong op conditions and so on. If all steps before "compile" have no issue, try to change compile strategy: start with launching without any constraints, and if it's good, add constraints gradually.

I wonder, is there any way to make DC give full response about fatal error, without this useless information about support.

Click to expand...

yes am using scripts. also me tried various compile options but getting same error. what to do else?

---------- Post added at 19:52 ---------- Previous post was at 19:51 ----------

vijay.mani884 said:

Hello,

First of all try and give the memory option for the tool. Check with your senior for the command for allocating memory, may be your design is not getting the sufficient memory for performing the synthesis.

Cheers.

Click to expand...

is there any command to give memory to synthesis tool?

Well, i think you should do a work around. do you have any other dc version available at your workplace? if yes, try and use that. as far as the command is concerned, i shall try and give you that. I need check it first.

Cheers

vijay.mani884 said:

Well, i think you should do a work around. do you have any other dc version available at your workplace? if yes, try and use that. as far as the command is concerned, i shall try and give you that. I need check it first.

Cheers

Click to expand...

No i dont have any other versions with me.

Hi,
You could tried without any sdc constraints, without any specific optimisations option, and execute one elaboration and synthesis. If that is ok, add one by one option and constraints.

rca said:

Hi,
You could tried without any sdc constraints, without any specific optimisations option, and execute one elaboration and synthesis. If that is ok, add one by one option and constraints.

Click to expand...

me tried by first only compile and all other options in compile which i knows but me getting same error. only in compile -no map its working but slack is very high in that case.

---------- Post added at 00:20 ---------- Previous post was at 00:18 ----------

rca said:

Hi,
You could tried without any sdc constraints, without any specific optimisations option, and execute one elaboration and synthesis. If that is ok, add one by one option and constraints.

Click to expand...

me tried by first only compile and all other options in compile which i knows but me getting same error. only in compile -no map its working but slack is very high in that case.

Could you removed the knowned options perhap, this design with this option could make this scratch?
Did you have a FPGA tool suite like quartus2 (free)? With this you could check your codes is correct, by executing a synthesis on your code.
Or if you access to an other synthesis tool?

rca said:

Could you removed the knowned options perhap, this design with this option could make this scratch?
Did you have a FPGA tool suite like quartus2 (free)? With this you could check your codes is correct, by executing a synthesis on your code.
Or if you access to an other synthesis tool?

Click to expand...

me not got what you want to say in 1st sentence.

me checked my coding in XILINX.

I means your script, only read the source code, and two commands, elaborate, synthesis, that's it.

---------- Post added at 21:06 ---------- Previous post was at 21:05 ----------

If your code is correct, in this case, you need to change the tools version, or and check the know issues of this tool version in solvnet.

rca said:

I means your script, only read the source code, and two commands, elaborate, synthesis, that's it.

---------- Post added at 21:06 ---------- Previous post was at 21:05 ----------

If your code is correct, in this case, you need to change the tools version, or and check the know issues of this tool version in solvnet.

Click to expand...

me not have access to solvnet. also in my script i did only three commands as u said just now.

alright, just try only one command first and see what you are getting, Read the verilog using only this command

"analyze -format verilog xyz.v" ---> this should give some basic linting errors if any. If this works fine, Then kindly, brief us the flow that you are using with scripts.

May be we can help you with that.

cheers