How page table maps virtual address spaces into real memory spaces

Hi all

Looking for an explanation on "page table" functionalities. How it works. What is its advantages?

Kindly illustrate with an example.

Hello saochandan:

In a simple language this is table which has entry of virtual address, physical address, size and access attributes.
So in one entry it includes all these four elements.

Virtual Address | Physical Address | Size| Access Attributes

For example:
0x20000000 is vritual address,
0x20000000 is physical address
0100B , size is specified 4^size, for example if size bits are 0100B then access size is 4^100 = 256KB
Access Attributes are read, write and execute permissions. Generally for two users, user and super user.
In case of powerpc 440 processors, there are instructions to access page tables, TLBWE (translate lookasize page write), For example this is the entry to map virtual address 0x00000000 to 0x00000000
In PPC 440 one TLB entry is of three words. This is the example , to uderstand the format of TLB entries you have to look into specific processor’s user manual.
=============================================================
addi r1,r0,0x1 ;tlb index 1
tlbre r0,r1,0x0000 ;reading data from tlb word0 and placed in r0
lis r0,0x0000 ;loading value 0 in to r0 with 16-bit shifted
ori r0,r0,0x0290 ;oring r0 with 0x0290 and result placed in r0
tlbwe r0,r1,0x0000 ;r0 value write in to tlb ,where as r1 holds tlb no

addi r1,r0,0x1 ;tlb index 1
tlbre r0,r1,0x0001 ;reading data from tlb word1 and placed in r0
lis r0,0x0000 ;loading value 0 in to r0 with 16-bit shifted
ori r0,r0,0x0000 ;oring r0 with 0x0000 and result placed in r0
tlbwe r0,r1,0x0001 ;r0 value write in to tlb ,where as r1 holds tlb no

addi r1,r0,0x1 ;tlb index 1
tlbre r0,r1,0x0002 ;reading data from tlb word2 and placed in r0
lis r0,0x0000 ;loading value 0 in to r0 with 16-bit shifted
ori r0,r0,0x013f ;oring r0 with 0x013F and result placed in r0
tlbwe r0,r1,0x0002 ;r0 value write in to tlb ,where as r1 holds tlb no

At the time of board initialization we do one to one mapping, that’s why you have seen 0x0 is mapped with 0x0. But OS like Linux itself manage the TLBs as per number of processes.
To read more about articles, tutorials and presentations, you can visit
http://embeddedcraft.org/

Thanks for answer and link. It's really very very helpful. I am trying to explore more in the context of ARM Cortex M3 process, I hope this would be similar to as you explained for PPC.