matching in ic layout design

hello
am new to analog layout design and i just started my career in the same
can any one explain about matching in ic layout design with sample exercises.
i came to know the various techniques available for matching and am not able
to understand them.so i want them in diagrams .

this might help.

this was my seminar report on Analog Layout Techniques in VLSI.

hello
am new to analog layout design and i just started my career at Sicon technologies.
Can any one explain about ic layout design with sample exercises.
i came to know the various techniques available for matching and am not able
to understand them.so i want them in diagrams .

RULES FOR MATCHING
TRANSISTORS:

Use identical finger geometries.

Use large active areas.

For voltage matching keep Vgst small.

For current matching keep Vgst large.

Use thin-oxide devices in preferance to the
thick-oxide devices.

Orient transistors in the same direction.

Place the transistors in the close proximity.



Keep the layout of the matched components as
compact as possible.

Use common centroid layouts.

Avoid using extremely short or narrow
transistors.

Place dummy segments on the ends of arrayed
transistors.

Place transistors in areas of low stress
gradients.


Place transistors well away from power devices.

Donot place contacts on top of active gate area.

Donot route metal across the active gate region.

Keep all junctions of deep diffusions far away
from active gate area.

Place precisely matched transistors on the axes
of symmetry of die.



Donot allow the NBL shadow to intersect the
active gate area.

Connect gate fingers using metal straps.

Consider using NMOS transistors rather than
the PMOS transistors.

read the book

Hastings, Alan. The Art of Analog Layout. New Jersey:
Prentice Hall, 2001.

This is good one !!