Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
How much value should i give for timing after synthesis?
I mean, if i have timing violation should i continue to floorplan place and route?
Thanks!
It depends which violation you are getting? Setup or Hold, if youare getting setup then you must fix them during your synthesis phase. If its a hold, you can continue with the PD (Physical Design). You can still ask the tool to give it a try to fix the hold using this command.
dc_shell> set_hold_fix <clock_name>
then reoptimize_design
pre timing need to get clear without any violation at logical synthesis stage. Then we can continue with that netlist at physical design stage.
If pre timing itself not clean we wont meet timing at the physical design stage even by doing repeated floorplan experiments.
vijay.mani884 ,
i have read the post, and from what i understand, before clk tree the clock is ideal, right? so there is no option that the required time will be longer than the arrival.
This means i should not see any hold violation, no?
So the reason we can't fix hold before clk tree is because it depends on the clk skew and latency? (unlike setup that depends also on clk period?)?
Setup analysis should be done first during synthesis as clock ideal and a very very small setup violation can be neglected and after that you can proceed to design planning,placement ,cts and after cts hold as well as setup should be fixed completely without any violations.....,after cts we mainly concentrate on hold analysis...,after this we go for Routing....,correct me if i am wrong
Cheers...,
The practical approach is to fix all setup violations before entering physical design flow. The main idea here is how much margin will you give to physical designer: if synthesis step sonsumes all the margin itsel, physical design will not converge on timing. below are some scenarios:
1 - If synthesis is done with all vth cells (hvt, svt, lvt), and you cannot close timing at synthesis, don't even think it will be solved at physical design step.
- This is because after you are at physical step, nothing will be ideal and parasitics will come into play!
- This is the worst case you would want!
2 - If you closed setup timing with hvt cells, then there is room to improve with svt & lvt cells at physical design step.
- In this situation some small slacks can be neglected, but ideally there should not be any setup violation.
3 - For hold fixing, normally you should not worry because of hold, as others said hold violations are fixed after CTS is done, and even after routing. However, there is one important thing here, lets assume you have "-10ns" hold slack after synthesis. Assuming a 200ps delay for hold fixing buffers (say delay cells), you need ~50 buffers to fix this violation. And if you have ~1000 hold violations similar to this, physical design flow may add 50000 delay fixing buffers, which will kill physical design engineers
Therefore we come to a rule of thumb: Small hold violations can be neglected, but bigger ones should be handled before entering place and route. By saying handled, I don't mean these hold fixing buffers may be added by synthesis people, but maybe a design change or constraints change can be required depending on the violation.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
