How to write a script for synthesis

Hi everybody,

Sory! because I put a stupid question but in fact I don't know how to begin with synthesis tools. Someone said me that I have to write a script file to run systhesis but I don't know how to write?

Pls hepp me or give me something !

Hi,

which synthesis tool do you need. If you use XST (Xilinx)
or Leonardo / Precision (Mentor) or Synplify (Synplicity) they
all have also graphical user interfaces ... besides the normaly
use tcl scripts if you want to run them in batch mode ... you can
create thos tcl scripts over the gui.

Andi

Hi tutx:

If you are a beginner, the best way is graphic not scripts. After you

familary with the graphic interface, then you can go with the scripts.

This book teach you alot about the scripts

ok sir, First understand the essence of synthesis ... get the basic right the rest will fall in place ........... Next decide on whether u are calling ur cards on FPGA or ASIC synthesis tool .... if u have absoultely no idea on what the whole thing is ... i would suggest u start from xilinx kit ...its free and it needs no scripting for synthesis although u will need some for constraining ur design but there is a good tutor in the kit itself which will help u a lot ...then u can start doing the more serious stuff like scripting to get ur job done

Thanks for all your advices !
However, the problem is not which tools I should chose for beginning. It is how should I do with the tools which my chef give me.

In my labo, we use only Cadence tools for VSLI design from modelsim to Synopsys tools. All of them works in UNIX. So it become big problem for me because I have never used UNIX and other tools in UNIX.

So what should I do now?

In My opinion, most serious engineering projected have been done in Unix based workstation. It's easier for you now, buy a cheap and old computer, download a simple version of Linux and start learning Linux.
Linux is one kind of Unix.

you can find some scripts of taped out project to learn them

set verbose 1 ;# 1 for verbose source and change_names commands

set rtl_language verilog ;# verilog or vhdl source RTL

set rundc 1 ;# 1 to start from RTL, 0 for existing db
set rtl2pg 0 ;# 1 for rtl to placed gates flow, 0 for rtl to gates

set use_clock_gating 0 ;# use RTL clock gating with Power Compiler
set integrated_cell 0 ;# tells Power Compiler to use integrated CG cell

set scan_ready 1 ;# A test ready compile will be performed
set scan_insertion 1 ;# Will cause the scan chains to be stitched
set numscanchains 4 ;# The number of scan chains to be implemented

set ultra 0 ;# Enable DC-Ultra (requires license)
set use_physopt 0 ;# Enable PhysOpt commands
set use_boundary_opt 0 ;# Enable boundary optimization
set force_wireload 0 ;# Use a custom Wire-load model
set flatten 0 ;# Remove all hierarchy from the design

set clk_period 5.5 ;# Target clock period in ns
set io_clk_period 5.5 ;# Target I/O clock period in ns
set clk_uncertainty 0.20 ;# Expected clock skew in ns
set min_latency 0 ;# Minimum clock latency under WCS
set max_latency 0 ;# Maximum clock latency under WCS

set apply_name_rules 1 ;# Change the names according the verilog names rule
set perled 0 ;# Applies the PERLED_MUX constant when parsing RTL

# ---------------------------

# Read in the technology specific scripts
if { $verbose } {
source -echo -verbose ./scripts/tsmc18.tcl
source -echo -verbose ./scripts/dont_use.tcl
} else {
source -echo ./scripts/tsmc18.tcl
source -echo ./scripts/dont_use.tcl
}

# Define the design library
define_design_lib work -path ./lib

if { $ultra } {
set_ultra_optimization true -force
}

if { $rundc } {
# Analyze the source RTL

set verilog_files { A946ESConstants.v A946ESParams.v \
a9esClkBlk.v a9esWRegDecoder.v a9esREG.v a9esFwd.v a9esRegC.v a9esIMM.v\
a9esIPipe.v a9esISyncr.v a9esMASeq.v a9esMainSeq.v a9esMem.v a9esPSR.v \
a9esPipeCtl.v a9esRegFwd.v a9esShALUADec.v a9esShALUTDec.v \
a9esShALUSeq.v a9esShALUCtl.v a9esWRegDec.v a9esMulCtl.v a9esCoreCtl.v \
a9esLU.v a9esSat.v a9esAU.v a9esArmShifter.v a9esShifter.v \
a9esSatTimes2.v a9esCLZ.v a9esExecute.v a9esRam3r2wSDff.v a9esByteRot.v\
a9esDAOut.v a9esIAOut.v a9esRegBank.v a9esMulDP.v a9esCoreDP.v \
a9esWptctl.v a9esDbgCommsctl.v a9esICEctl.v a9esTapScanctl.v \
a9esDbgctl.v a9esWptdp.v a9esDbgCommsdp.v a9esICEdp.v a9esTapScandp.v \
a9esDbgdp.v a9esDbg.v ARM9ES.v A946ESRegFile16x40.v A946ESFifo.v \
A946ESAHBBiuWb.v A946ESCPIntf.v A946ESCaRepl.v A946ESProtUnit.v \
A946ESClkGate.v A946ESETMBuf.v A946ESHitDet.v A946ESDaCntrl.v \
A946ESInsCntrl.v A946ESIntClken.v A946ESLdmStmTrk.v A946ESCp15.v \
A946ESCaTCMCntrl.v A946ESCore.v A946ESDValidMux.v A946ESIValidMux.v \
A946ESDValid.v A946ESIValid.v A946ESRBistShell.v A946ESDCache.v \
A946ESDTag.v A946ESDDirty.v A946ESICache.v A946ESITag.v A946ESRBistCtl.v \
ARM946ES.v }

set vhdl_files { a9esComponents.vhd a9esConstants.vhd a9esSat.vhd \
a9esArmShifter.vhd a9esDbgCommsctl.vhd a9esWptctl.vhd \
a9esDbgCommsdp.vhd a9esWptdp.vhd a9esISyncr.vhd a9esFwd.vhd \
a9esREG.vhd a9esRegC.vhd a9esShALUTDec.vhd a9esShALUSeq.vhd \
a9esShALUADec.vhd a9esWRegDecoder.vhd a9esAU.vhd a9esCLZ.vhd \
a9esLU.vhd a9esSatTimes2.vhd a9esShifter.vhd a9esRam3r2wSDff.vhd \
a9esICEctl.vhd a9esTapScanctl.vhd a9esICEdp.vhd a9esTapScandp.vhd \
a9esIMM.vhd a9esIPipe.vhd a9esMASeq.vhd a9esMainSeq.vhd \
a9esMem.vhd a9esMulCtl.vhd a9esPSR.vhd a9esPipeCtl.vhd \
a9esRegFwd.vhd a9esShALUCtl.vhd a9esWRegDec.vhd a9esByteRot.vhd \
a9esDAOut.vhd a9esExecute.vhd a9esIAOut.vhd a9esMulDP.vhd \
a9esRegBank.vhd a9esDbgctl.vhd a9esDbgdp.vhd a9esDbg.vhd \
a9esCoreDP.vhd a9esCoreCtl.vhd a9esClkBlk.vhd ARM9ES.vhd \
A946ESParams.vhd A946ESConstants.vhd A946ESFunctions.vhd \
A946ESComponents.vhd A946ESFifo.vhd A946ESAHBBiuWb.vhd \
A946ESHitDet.vhd A946ESCaRepl.vhd A946ESProtUnit.vhd \
A946ESDaCntrl.vhd A946ESInsCntrl.vhd A946ESIntClken.vhd \
A946ESLdmStmTrk.vhd A946ESCp15.vhd A946ESCaTCMCntrl.vhd \
A946ESCPIntf.vhd A946ESETMBuf.vhd A946ESClkGate.vhd \
A946ESCore.vhd A946ESRAMComponents.vhd A946ESICache.vhd \
A946ESITag.vhd A946ESDCache.vhd \
A946ESDTag.vhd A946ESDDirty.vhd A946ESDValidMux.vhd \
A946ESIValidMux.vhd A946ESDValid.vhd A946ESIValid.vhd \
A946ESRBistShell.vhd A946ESRBistCtl.vhd ARM946ES.vhd }

if { $rtl_language == "verilog" } {
if { $perled } {
analyze -f verilog -define PERLED_MUX $verilog_files
} else {
analyze -f verilog $verilog_files
}
} else {
if { $perled } {
analyze -f vhdl -define PERLED_MUX $vhdl_files
} else {
analyze -f vhdl $vhdl_files
}
}

if { $use_clock_gating } {
if { $scan_ready } {
if { $integrated_cell } {
set_clock_gating_style -sequential_cell latch \
-positive_edge_logic {integrated:TLATNTSCAX8} \
-control_point before -control_signal scan_enable \
-max_fanout 8
} else {
set_clock_gating_style -sequential_cell latch \
-control_point before -control_signal scan_enable \
-max_fanout 8
}
} else {
set_clock_gating_style -sequential_cell latch -setup 0 -hold 0
}
elaborate -update -gate_clock ARM946ES
} else {
elaborate -update ARM946ES
}

# Uniquify and link the design
current_design ARM946ES
uniquify
link

# Identify the scan style and hookup the testports of all clock gating elements
if { $scan_ready } {
set_scan_configuration -methodology full_scan -style multiplexed_flip_flop
set_scan_signal test_scan_enable -port SCANEN
create_net SCANEN
connect_net SCANEN [find port SCANEN]
if { $use_clock_gating } {
hookup_testports
}
}

redirect ./report/ARM946ES.check_design {check_design}

create_clock -period $clk_period CLK
set_clock_uncertainty -setup $clk_uncertainty CLK
set_clock_uncertainty -hold $clk_uncertainty CLK
set_clock_transition 0 CLK

create_clock -period $clk_period UnGatedCLK
set_clock_uncertainty -setup $clk_uncertainty UnGatedCLK
set_clock_uncertainty -hold $clk_uncertainty UnGatedCLK
set_clock_transition 0 UnGatedCLK

# Identify the high fanout nets and set the context for the design
set high_fanout [list CLK UnGatedCLK SCANEN HRESETn DBGnTRST DBGTCKEN]
set_ideal_net $high_fanout

set_load $load_value [list [all_outputs]]
set_driving_cell -cell $driving_cell_name -pin $driving_cell_pin [\
list [remove_from_collection [all_inputs] $high_fanout]]

# Set the IO timing
if { $verbose } {
source -echo -verbose scripts/arm946es_constraints.tcl
} else {
source -echo scripts/arm946es_constraints.tcl
}

# Identify wire load model and operating conditions
if { $force_wireload } {
set_wire_load_model -name $wireload_model -library $wireload_library
set_wire_load_mode top
} else {
set auto_wire_load_selection true
set_wire_load_mode top
}

# Set the operating conditions
set_operating_conditions slow

# Set specific compile options
set_max_area 0
set_max_transition 1 ARM946ES
set_resource_implementation use_fastest
foreach_in_collection design [get_designs "*"] {
current_design $design
set_fix_multiple_port_nets -all -buffer_constants
echo " ** Setting set_fix_multiple_port_nets -all -buffer_constants ** "
}
current_design ARM946ES
set_critical_range 0.2 ARM946ES

# Propagate constraints if using clock gating
if { $use_clock_gating } {
propagate_constraints -gate_clock
}

# Create test ports for scan in and scan out
current_design ARM946ES
if { $scan_insertion } {
for { set i 1 } {$i <= $numscanchains} {incr i} {
set port_name [ format "%s%s" SCANIN $i ]
create_port $port_name -direction in
set_scan_signal test_scan_in -port $port_name
}
for { set i 1 } {$i <= $numscanchains} {incr i} {
set port_name [ format "%s%s" SCANOUT $i ]
create_port $port_name -direction out
set_scan_signal test_scan_out -port $port_name
}
}

# Compile the ARM946E-S top down
current_design ARM946ES

redirect ./report/ARM946ES.check_timing {check_timing}

if { $flatten } {
ungroup -all -flatten
}

if { $rtl2pg } {
read_pdef ./floorplan/ARM946ES.pdef
if { $scan_ready } {
compile_physical -scan
} else {
compile_physical
}
} else {
if { $scan_ready } {
if { $use_boundary_opt } {
compile -boundary_optimization -map_effort medium -scan -area_effort none
} else {
compile -scan -map_effort medium -area_effort none
}
} else {
if { $use_boundary_opt } {
compile -boundary_optimization -map_effort medium -area_effort none
} else {
compile -map_effort medium -area_effort none
}
}
}

} else {

# Read existing DB
read_db ./db/ARM946ES-existing.db
current_design ARM946ES
link
}

if { $use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
read_pdef ./floorplan/ARM946ES.pdef
set physopt_pnet_partial_blockage_layer_names {METAL1 METAL2}
physopt -timing_driven_congestion -area_recovery
#Remove PhysOpt license
remove_license PhysOpt
}

# Insert scan into the design
if { $scan_insertion } {

set_test_hold 1 TESTMODE
set_scan_configuration -methodology full_scan -style multiplexed_flip_flop\
-chain_count $numscanchains -dedicated_scan_ports true -add_lockup true\
-clock_mixing mix_clocks_not_edges -replace false

set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 90
set test_default_period 100

set test_stil_multiclock_capture_procedures true

set test_stil_netlist_format verilog

create_test_clock [list UnGatedCLK CLK ] -period 100 -waveform {45 55}

# reapply set_fix_multiple_port_nets
foreach_in_collection design [get_designs "*"] {
current_design $design
set_fix_multiple_port_nets -all -buffer_constants
echo " ** Setting set_fix_multiple_port_nets -all -buffer_constants ** "
}
current_design ARM946ES

redirect ./report/ARM946ES-preinsert.dft { check_dft }

if { $use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
insert_dft -physical -map_effort high
physopt -eco -incr
#Remove PhysOpt license
remove_license PhysOpt
} else {
insert_dft -map_effort high
#perform incremental compile to remove assign statements
compile -incremental_mapping -map_effort low -area_effort none
}


redirect ./report/ARM946ES-physical.dft { check_dft }
redirect ./report/ARM946ES.scanpath { report_test -scan_path }
}

if { $use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
check_legality
#Remove PhysOpt license
remove_license PhysOpt
}

if { $apply_name_rules } {
if { $verbose } {
change_names -rules verilog -hierarchy -verbose > ./report/ARM946ES.change-names
} else {
change_names -rules verilog -hierarchy > ./report/ARM946ES.change-names
}
}

# Save the design
write -f db -hierarchy -o ./db/ARM946ES.db
write -f verilog -hierarchy -o ./db/ARM946ES.v
write_sdc -version 1.2 ./db/ARM946ES.sdc

# Report on the design

# Generate an area report for each module
redirect ./report/ARM946ES.area { echo "" }
foreach_in_collection design [get_designs "*"] {
current_design $design
redirect -append ./report/ARM946ES.area { report_area }
}
current_design ARM946ES

# Generate general reports
redirect ./report/ARM946ES.hier { report_hierarchy }
redirect ./report/ARM946ES.qor { report_qor }
redirect ./report/ARM946ES.path-group { report_path_group }
redirect ./report/ARM946ES.detail { report_design }
redirect -append ./report/ARM946ES.detail { report_clock -attributes -skew }
redirect ./report/ARM946ES.port { report_port -verbose }

# Generate fanout reports for the high fanout nets
redirect ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from CLK }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from UnGatedCLK }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from HRESETn }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from DBGnTRST }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from DBGTCKEN }
redirect -append ./report/ARM946ES.fanout { report_transitive_fanout -nosplit -from SCANEN }

# Look for latches and combinational loops
redirect ./report/ARM946ES.latches { all_registers -level_sensitive }
redirect ./report/ARM946ES.loops { report_timing -loops }

# Generate timing reports
redirect ./report/ARM946ES.input-max-timing { report_timing -delay max -max_paths 500 -from [all_inputs]}
redirect ./report/ARM946ES.output-max-timing { report_timing -delay max -max_paths 500 -to [all_outputs]}
redirect ./report/ARM946ES.reg2reg-max-timing { report_timing -delay max -max_paths 500 -from [ all_registers -clock_pins ] -to [ all_registers -data_pins ] }
redirect ./report/ARM946ES.vio { report_constraint -all_violators }

if { $use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
redirect ./report/ARM946ES.congestion { report_congestion -congestion_effort medium }
#Remove PhysOpt license
remove_license PhysOpt
}

if {$use_physopt } {
#Make sure we have PhysOpt license
remove_license PhysOpt
set PhysOpt_status [ get_license PhysOpt ]
while { $PhysOpt_status == 0 } {
redirect /dev/null { set PhysOpt_status [get_license PhysOpt] }
}
set pdefin_use_nameprefix false
write_pdef -v3.0 -output ./db/ARM946ES.pdef
#Remove PhysOpt license
remove_license PhysOpt
}

quit

set_output_delay 0 -min -clock CLK [remove_from_collection [all_outputs] GateTheCLK]
set_output_delay [expr ( ${clk_period} * 0.1 - $min_latency ) ] -max -clock CLK [remove_from_collection [all_outputs] GateTheCLK]

# CLOCK GATING

set_output_delay 0 -min -clock UnGatedCLK [ list GateTheCLK ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.80) * ${io_clk_period}) - $min_latency)] -max -clock UnGatedCLK [ list GateTheCLK ]

# AHB interface

set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list HADDR ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list HTRANS ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list HBURST ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list HWRITE ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list HSIZE ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list HPROT ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list HWDATA ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list HBUSREQ ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list HLOCK ]

# TCM Interface
set_output_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) - $min_latency)] -max -clock CLK [ list ITCMWData ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) - $min_latency)] -max -clock CLK [ list ITCMWEn ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) - $min_latency)] -max -clock CLK [ list ITCMEn ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) - $min_latency)] -max -clock CLK [ list ITCMAdrs ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) - $min_latency)] -max -clock CLK [ list DTCMWData ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) - $min_latency)] -max -clock CLK [ list DTCMWEn ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) - $min_latency)] -max -clock CLK [ list DTCMEn ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) - $min_latency)] -max -clock CLK [ list DTCMAdrs ]

# Coprocessor interface

set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list CPCLKEN ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list CPINSTR ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list CPDOUT ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list CPPASS ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list CPLATECANCEL ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list CPTBIT ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list nCPMREQ ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list nCPTRANS ]

# Debug interface

set_output_delay [expr ( ${clk_period} - ((1 - 0.40) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list COMMRX ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.40) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list COMMTX ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.40) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGACK ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.55) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGRQI ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGINSTREXEC ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.20) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGRNG ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.35) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGTDO ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.75) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGIR ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGSCREG ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGTAPSM ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.60) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGnTDOEN ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.80) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list DBGSDIN ]

# ETM interface

set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMBIGEND ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMHIVECS ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMnWAIT ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMIA ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMInMREQ ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMISEQ ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMITBIT ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMIABORT ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMID31To25 ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMID15To11 ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMDA ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMWDATA ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMDMAS ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMDMORE ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMDnMREQ ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMDnRW ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMDSEQ ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMRDATA ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMDABORT ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMCHSD ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMCHSE ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMLATECANCEL ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMPASS ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMDBGACK ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMINSTREXEC ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMRNGOUT ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMINSTRVALID ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMPROCID ]
set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list ETMPROCIDWR ]

# Misc Signals

set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency )] -max -clock CLK [ list BIGENDOUT ]

# Scan Interface

set_output_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) - $min_latency)] -max -clock CLK [ list SO ]

# All min delay

set_input_delay 0 -min -clock CLK [remove_from_collection [all_inputs] UnGatedCLK]

set_input_delay [expr ( ${clk_period} - ((1 - 0.05) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DCacheSize ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.05) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list ICacheSize ]

# AHB interface

# the following are for a 1:1 CLK HCLK ratio
set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list HREADY ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list HRESP ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.60) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list HRDATA ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list HGRANT ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list HRESETn ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.15) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list HCLKEN ]

# Misc Signals

set_input_delay [expr ( ${clk_period} - ((1 - 0.85) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list nFIQ ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.85) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list nIRQ ]

# Initialisation Control

set_input_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list VINITHI ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list INITRAM ]

# Coprocessor interface signals

set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list CPDIN ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list CHSDE ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list CHSEX ]

# TCM Interface
set_input_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list ITCMRData ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.70) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list DTCMRData ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list PhyITCMSize ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list PhyDTCMSize ]

# Debug interface

set_input_delay [expr ( ${clk_period} - ((1 - 0.65) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DBGEN ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.80) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list EDBGRQ ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.85) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DBGEXT ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DBGIEBKPT ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DBGDEWPT ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.75) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DBGnTRST ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DBGTCKEN ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.75) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DBGTDI ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.75) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DBGTMS ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.10) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list DBGSDOUT ]

set_input_delay [expr ( ${clk_period} - ((1 - 0.65) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list TAPID ]

# ETM interface

set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list ETMEN ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.50) * ${io_clk_period}) + $max_latency )] -max -clock CLK [ list ETMFIFOFULL ]

# Scan Interface

set_input_delay [expr ( ${clk_period} - ((1 - 0.05) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list SI ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.05) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list SCANEN ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.05) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list TESTMODE ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.05) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list SERIALEN ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.05) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list TESTEN ]
set_input_delay [expr ( ${clk_period} - ((1 - 0.05) * ${io_clk_period}) + $max_latency)] -max -clock CLK [ list INnotEXTEST ]

remove_input_delay CLK
remove_input_delay UnGatedCLK

this r come paper which deal with scripting for eda tools
thnaks

You can study the synopsys sold document.

u may study the script from the sold of the synosys

you can take the above script i posted as a template.

goto synopsys solvnet to read their

1. white papers.
2. examples.
3. tutorials.

If you work in a company, cd into the company database and browse through the past designs, that's a goldmine for catching up the others and learn the company's coding styles.

copy a templet and make a correct modify !

wadaye said:

Hi tutx:

If you are a beginner, the best way is graphic not scripts. After you

familary with the graphic interface, then you can go with the scripts.

Click to expand...

There is not much graphic in synthesis tool !

Yes, SOLD is a good place to start learning

Just my two cents on synthesis...

Sorry, but in my opinion SOLD is the WORST way to learn synthesis. The amount of info is huge for a beginner. People that recommned reading SOLD to a beginner make a major mistake in my opinion. The beginner is faced with a lot of info that's overwhelming, may start on the wrong foot, get scarried with it and think of synthesis as something he/she will never be able to learn. This is what happened to me.
SOLD is a comprehensive document. Any manual has to cover all the details, regardles of how important of unimportant they are. Writers of manuals have the obligation to cover any aspect of the problem so that user won't complain. Manuals are generally made for experienced users that already know what they are doing
As a beginner one is not able to know whether things explained in chapter x will be very useful in practice or completely unuseful. And he/she could focus too much on something unimportant and just browse through important stuff. After all, there are thousands of pages only for the Design Compiler documentation. One can't remember thousands of pages, especially if it is completelky new stuff.
But this is just my opinion. Learning synthesis may be vary painful sometimes.

And a few comments:

dumeHCM said:

There is not much graphic in synthesis tool !

Click to expand...

Yeah, but don't you wish there was some? Wouldn't it be nice to have a nice treeview showing all the designs currently in memory? And to set constraints by clicking on checkboxes and filling editboxes? And to go to an Options/Compile menu and set all the compilation options by using radiobuttons and editboxes and stuff, and having a tooltip showing a quick explanation for every option instead of using the man command, or even better, context-sensitive help? If not, it means you find some intrinsic masochistic pleasure in writing scripts using that "awesome" vim editor, which I can't possibly understand.

HCM_bucat said:

In My opinion, most serious engineering projected have been done in Unix based workstation. It's easier for you now, buy a cheap and old computer, download a simple version of Linux and start learning Linux.
Linux is one kind of Unix.

Click to expand...

Unix is nothing but a necessary evil.