[SOLVED] MosFET Models Question For Analog Designer

I was wondering how are analog designers coping up with the issues arising due to the scaling of technology where hand calculations just dont match simulations .
My Doubts is that, How do u select a model for hand calculation for a specific technology. For example Square law in sat doesnt hold for .18um. So How u select model, Do u go for sakurai Model. How to designer Judge W/L ratio for a particular technology.

Hello Shabazsyed
I read your terms. I think that some of engineers prefer to choose design methodologies for designing CMOS circuits in nano-scale circuits. For example, gm/Id is a design methodology that is used by engineers. This design method is performed using simulation softwares like Hspice. So you can design a nano-scale circuit without challenging complex CMOS model equations. You can find further reading by searching the phrase "gm/Id Methodology" in search engines.

But i heard Hand Calculations are done b4 simulations to get almost close to simulation result . . Please See this link and see if u can help me out here.
https://www.edaboard.com/threads/251260/

shabazsyed said:

i heard Hand Calculations are done b4 simulations to get almost close to simulation result

Click to expand...

At least in sub-micron processes you have to consider a lot of effects (velocity saturation, VFMR, CLM) which can be approximated by hand calculations, this results in rather complex connections, however. Binkley e.g. suggests and shows Excel tables for such extensive calculations.

David M. Binkley "Tradeoffs and Optimization in Analog CMOS Design"
**broken link removed**

I've been designing IC products and ASICs for almost 30 years
and I haven't done a hand calculation for a transistor operating
point since college. I have a gut feel for how the devices work,
I have the equipment to verify the DC models are reasonable,
when there's a question, and that's been good enough. I have
too much to do, to do things the hard way.

dick_freebird said:

I've been designing IC products and ASICs for almost 30 years
and I haven't done a hand calculation for a transistor operating
point since college. I have a gut feel for how the devices work,
I have the equipment to verify the DC models are reasonable,
when there's a question, and that's been good enough. I have
too much to do, to do things the hard way.

Click to expand...

Thanks for replying. Are u suggesting that i simulate untill i get desired currents. How do u handle Sub Micron Devices. I am a fresher, any suggestions and help is appreciated.

please give the link from where could I download Hspice software

www.hspice.com ;-)

thanx erikl
please tell is it possible to use CNTFETs as Gate material using HSpice else suggest some-other software.

is it possible to use CNTFETs as Gate material?

Depends on what you want to do:

If you want to run circuit analysis, you need a model file of a CNTFET. In this case, the CNT gate material is already considered.

If you want to run device analysis, you need a 2D- or 3D-description of the device, incl. all its geometrical & physical parameters, and TCAD device simulator software like Taurus Medici, Sentaurus Device, Silvaco ATLAS or others.

thanx budy,
basically, i'm trying to get simulation results for a SRAM cell.

shabazsyed said:

I was wondering how are analog designers coping up with the issues arising due to the scaling of technology where hand calculations just dont match simulations .
My Doubts is that, How do u select a model for hand calculation for a specific technology. For example Square law in sat doesnt hold for .18um. So How u select model, Do u go for sakurai Model. How to designer Judge W/L ratio for a particular technology.

Click to expand...

I'd say designers use their intuition, experience, rules-of-thumb calculations (maybe using gm/Id charts), to come up with a rough sizing of the circuit, and then check it by simulation. If specs are loose this is sufficient even in modern technologies. Equations are also helpful to guide topological modifications of the circuit.
If specs are tight, most designers continue with tweak-simulate-tweak instead of setting up detailed equations, because equation-based methods become infeasible very quickly when you have to include second-order effects, corners, trade-offs, process variation, and transient simulation.
You shouldn't use tuning as a replacement for the initial sizing, but for getting high performance designs it's perfect. Optimization software can often do it faster and better than designers. My company (MunEDA) works in this field, and we call it "numerical sizing".