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[SOLVED] delay value differ in same cell

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jsathish.challenge

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Hi all,
In our .lib ,for example for AND gate has 2 inputs.It has below arcs
A-->X
B-->X
I have a one doubt on the cell delay value,why the cell delay is different between A to X and B to X for same slew and load....



Regards,
sathish
 

Gate delay is measured between 50% of input transition to the corresponding 50% of output transition. Transition time is calculation using RC. C is the capacitive load seen at output of the gate. R is the resistance of the charging/discharging path i.e. on time resistance of the transistors that charges output load. Different inputs switch on the different transistors. Hence on time resistance is different. So the delay is different.
 
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