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[SOLVED] Nmos Drain Spice Simulation and Hand Calculations Comparision

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shabazsyed

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Hello Guys ,
I am trying to verify my Hand Calculations and Spice Results. But the simulated results are less than Calculated. Its TSMC .35um Tech.
Spice Code.
***8
vdg vds 0 dc 5
vff vgs 0 dc 5
vdum vds b dc 0

mn1 b vgs 0 0 nmos w=1u l=.4u

.include moslh.md
.dc vdg 0 5 .00005 vff 1 5 1
.control

reset

run

plot i(vdum)
.endc

.end




Capture.PNG
My Calculated Results
Capture.PNG
Simulated Results.
Y is Calculated Result differing From Spice Results?
Any Suggestions.
Eagerly Waiting For Some replies.
Thanx
 

Do you imagine that your hand calculations (and importantly
the underlying model) include all of the nonidealities of real
short-channel devices?

In my courses, back in the day, the first thing mentioned
was all of the assumptions made to render hand analysis
tractable.

If the SPICE model is matched to data then these aspects
are embedded, not neglected. Of course that requires
some trust in the foundry model.
 
Thanx for Reply. Ok i Guess u r saying that i am not considering various other Parameters for calculations, But i read on internet and from the various books that + or - 5% variations only happen between Spice and Hand Calculations even if i ignore those parameters. Is it because the technology is .35um and that square law formula holds only for Large devices. If it is, then how to go on designing Circuits @ this level because we need W/L for Particular current in circuit or Current Mirroring or so.. So how do i Decide it
 
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    junky1

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Capture.PNGCapture1.PNG
I made Some new improvements today , Now my calculated result is exactly Twice than what i simulated..... I suspect there is something wrong with my Model File.
 

I guess i am not considering velocity saturation effect and effective mobility right?
 

shabazsyed said:
I guess i am not considering velocity saturation effect and effective mobility right?
Click to expand...

Already apart from these (and other) effects, you can see deviations from your hand calculations which are by far larger than those you found: just by changing the gate length (keeping the same W/L ratio) -- at least in strong inversion operation, s. the foll. figure from David M. Binkley "Tradeoffs and Optimization in Analog CMOS Design" :


The a.m. book also trades extensively velocity saturation and VFMR (vertical field mobility reduction) effects, as well as CLM (channel length modulation) effect.
 

this is Y i had that NMOS model question. Coz i calculated drain current using level 1 eqn but simulations are done using level 49.... So i guess u r trying to tel me @ sub micron i cant calculate current and have to depend on simulators and my model? So how do designers calculate or find W/L ratio for a particular current in circuit? Thanks
 

shabazsyed said:
... how do designers calculate or find W/L ratio for a particular current in circuit?
Click to expand...

E.g. with extended "hand calculations" using Excel tables, s. the a.m. book!
 

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