Arithmetic and Logic Unit (ALU) design / data-gating

Hello,
Just wondering if data-gating is often used in static logic ALUs and what the advantages/disadvantages are? For example, in an ALU comprising an adder and a logic block (AND/OR/XOR), is the data to the logic block or adder gated and activated only when needed during specific cylcles or do the logic block and adder evaluate simultaneously every cycle regardless of whether the output is utilized. One advantage that comes to mind of simultaneous activation of both units is that no additional resources (switches, clock signals) would be required for data gating. Also, since the logic is static the data activity is only 10-20% wheras with data gating additional resources would be required to determine when data gate(s) should be activated.
Any thoughts on this would be immensely appreciated.

I dont think there is a need for gating since gating would be helpful only if there is a clock involved. In that case, dynamic power consumption becomes the issue and a gated logic would be helpful. So, I think your point is correct.