[SOLVED] Why do we use a diode (i.e. connect gate and drain) in a current mirror?

In a current mirror we connect the gate and drain (or base and collector so that we have a diode). But if you need the same current in the output it is sufficient if we have same voltage at the gate (or base). That means even if we don't connect gate and drain we will have equal voltage at the gate. Then why should we connect gate and drain?

Thanks in advance.:razz::razz:

iVenky said:

... Then why should we connect gate and drain?

Click to expand...

Counterquestion: why not? It's the simplest circuit solution

• to ensure the "master" transistor works in saturation region (MOSFET), i.e. in active mode (gain)
• ... and just consumes a relatively small part of the available power supply voltage

... and just consumes a relatively small part of the available power supply voltage

Click to expand...

I understand the first sentence but how do you say that it consumes small part of power supply voltage?

iVenky said:

In a current mirror we connect the gate and drain (or base and collector so that we have a diode). But if you need the same current in the output it is sufficient if we have same voltage at the gate (or base). That means even if we don't connect gate and drain we will have equal voltage at the gate. Then why should we connect gate and drain?

Thanks in advance.:razz::razz:

Click to expand...

If you don't connect the gate to the drain, then the gate is floating. By connecting the drain, you are using the drain voltage to bias the gate.

iVenky said:

... how do you say that it consumes small part of power supply voltage?

Click to expand...

For CMOS processes ≧ 1µm Vth ≪ Vsupply
For CMOS processes < 1µm Vth < Vsupply
For CMOS processes ≦ 100nm Vth < Vsupply, but already a considerable part of Vsupply

... so I should relativise my statement and discard the word "small" from my above pronouncement for process technologies ≦ 100nm .
Could you, possibly, agree? ;-)

erikl said:

For CMOS processes ≧ 1µm Vth ≪ Vsupply
For CMOS processes < 1µm Vth < Vsupply
For CMOS processes ≦ 100nm Vth < Vsupply, but already a considerable part of Vsupply

... so I should relativise my statement and discard the word "small" from my above pronouncement for process technologies ≦ 100nm .
Could you, possibly, agree? ;-)

Click to expand...

I mean how does connecting the gate and drain helps you in consuming small amount of power?

---------- Post added at 19:52 ---------- Previous post was at 19:51 ----------

checkmate said:

If you don't connect the gate to the drain, then the gate is floating. By connecting the drain, you are using the drain voltage to bias the gate.

Click to expand...

Okay can I give external bias and still not connect gate and drain?

iVenky said:

I mean how does connecting the gate and drain helps you in consuming small amount of power?

---------- Post added at 19:52 ---------- Previous post was at 19:51 ----------



Okay can I give external bias and still not connect gate and drain?

Click to expand...

The good thing about a diode is that it is given a current, and generates a voltage according to it's I-V characteristics. You can change its current load, and it will generate a voltage accordingly.
So of course you can provide an external bias voltage, but you'd better make sure this voltage is identical to that of the diode, otherwise you will just push the current source for your current mirror current reference into linear region. And your external bias also has to track changes in current due to PVT variations as well.

iVenky said:

I mean how does connecting the gate and drain helps you in consuming small amount of power?

Click to expand...

It doesn't help for such purpose. There's no context between this circuit method and power consumption.

This "diode connection" just biases the MOSFET

1. in saturation region
2. in moderate inversion operation mode