ATPG Test Coverage DFT

Hi,

I had two analog blocks in my design, which were black box due to which the coverage was very low.

So i added wrapper flops at all the inputs and outputs, but still the coverage is not improved...

Can anyone suggest what should be done to improve the coverage??

Hi,

i ) For the analog macros, if your analog macro has the test mode / scan mode compatible please use that model , so that during test mode it will drive the outputs to know states instead of unknown values. This will help some percent of faults will be testable.
If you don’t have / get any model then check with the second approach.
ii) Another approach is, if you have rights to add control points,
For the analog macro input ports, add the simple mux or logic gates such that analog macro should be in shutdown / off state. This you can make via your scan mode / test mode signals.
Also add the same simple mux or logic gates on the output ports so that it will drive some known value during scan mode / test mode.
Else,
Add the control muxes at the output ports and connect the one input of mux to analog o/p and other input to the existing scan flop output which is in the same module /design which operates in the same clock domain. So that during scan mode the mux will select the scan flop so that the shadow logic on the output side of analog macro will be testable.

Hi,
Any results / updates from your side?

No the logic i was adding created more faults...
So there was no much improvement in coverage...