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[Hard] What is the pros/cons of more stages pipelining

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TuAtAu

TuAtAu

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100 Stages of pipelining better?
or 5 Stages of pipelining better?
A lots of arguments.

SO, the question is : What is the cons of more stages pipelining.

My current research is :
1. More Stages pros: has better performance and troughtput.
2. More Stages cons: difficult to design due to complexity.

3. Less Stages : vice versa.

//I surfed the web and only found those.. But I am sure that there is a reason why so many processors done in lesser Stages compared to More stages..

Anyone have any idea?
 

There is another shortpoint of more stage: if there is a jump operation, and you need clear up all the pipelines in all the stags, then more cycle will be wasted, compare to less pipeline sta
 
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    TuAtAu

    TuAtAu

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Ya cost! Is It heat will also increase? Use more power to run right?
 

YES good point!
More pipes~ means more chances to causing hazards! data hazards etc.

example 10 pipes~ mean amount the 10 instruction if read/write the same register in that sequence~ then hazards will occur!

good point Simranjeet Singh!
 

yx.yang said:
There is another shortpoint of more stage: if there is a jump operation, and you need clear up all the pipelines in all the stags, then more cycle will be wasted, compare to less pipeline sta
Click to expand...
I am sorry I am disturbing the topic but I have to ask. Is there any way to prevent this to happen?
 

yes~ branch prediction~ if u correctly predict~ it no need to clear up~ try to GOOGLE: BRANCH PREDICTION
 

Latency is proportional to the number of stages. In some market segments (e.g. high-frequency stock trading), latency is king.
 
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    TuAtAu

    TuAtAu

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skyfaye said:
Latency is proportional to the number of stages. In some market segments (e.g. high-frequency stock trading), latency is king.
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latency? I dont get it, since all operation is done in each stage, so after the 1st flow: means the 1st instructions finished flow through all the stages, then the following instructions should be complete in 1 Clock cycle what? and the clock cycle can be minimize since there is a lot of stages with tiny fractional operation..

Is it your latency refer to the 1st instruction to be completed?
 

More pipeline stages gets you more complications unless you balance all pipelining stages properly. If all stages aren't properly balanced then throughput of system doesn't increase , it gets decreased. More stages increases time by a signal taken to pass all stages , thus increase in latency.
 
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    TuAtAu

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jeet_asic said:
More pipeline stages gets you more complications unless you balance all pipelining stages properly. If all stages aren't properly balanced then throughput of system doesn't increase , it gets decreased. More stages increases time by a signal taken to pass all stages , thus increase in latency.
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In other word, If you don't want to balance all the pipelining stages properly, then do not try to design so many stages. Did I hit the point?
 

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