Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Verilog Weird Error with logical correct code but has errors in compilation

Status
Not open for further replies.
N

nyogtha

Newbie level 2
Newbie level 2
Joined
Apr 21, 2012
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,322
Hello.I got an assignment for my university.I have to make an Adder/Subtractor with the ability to add or subtract 2 numbers with 8 digits named X and Y and to change mode with M.The final Carry must be outputed as G,the Results as R and i added an overflow check called V.I made that code :
Code: 
module BCD_FSA11(X,Y,M,R,G,V);

input [7:0] X,Y;
input M;
output [7:0] R;
output G;
output V;
wire[6:0] C;
wire [7:0] O;

O[0]= M^Y[0];
R[0]= M^X[0]^O[0];
C[0]=(X[0]& O[0]) | (X[0] & M) | (O[0] & M);
O[1]= M ^ Y[1];
R[1]= C[0]^X[1]^O[1];
C[1]=(X[1]&O[1]) | (X[1] & C[0]) | (C[0] & O[1]);
O[2]= M^Y[2];
R[2]= C[1]^X[2]^O[2];
C[2]=(X[2]&O[2]) | (X[2] & C[1]) | (C[1] & O[2]);
O[3]= M^Y[3];
R[3]=C[2]^X[3]^O[3];
C[3]=(X[3]&O[3]) | (X[3] & C[2]) | (C[2] & O[3]);
O[4]=M^Y[4];
R[4]=C[3]^X[4]^O[4];
C[4]=(X[4]&O[4]) | (X[4] & C[3]) | (C[3] & O[4]);
O[5]=M^Y[5];
R[5]=C[4]^X[5]^O[5];
C[5]=(X[5]&O[5]) | (X[5] & C[4]) | (C[4] & O[5]);
O[6]=M^Y[6];
R[6]=C[5]^X[6]^O[6];
C[6]=(X[6]&O[6]) | (X[6] & C[5]) | (C[5] & O[6]);
O[7]=M^Y[7];
R[7]=C[6]^X[7]^O[7];
G=( X[7]&O[7]) | (X[7] & C[6]) | (C[6] & O[7]);
V=C[6]^G;
endmodule

module testbench();
reg [7:0] A,B;
reg C;
wire [7:0] X;
wire Y;
wire Z;
BCD_FSA11 x9(A,B,C,X,Y,Z);
initial begin
A=$random;
B=$random;
C=$random;
#600 A=$random;
B=$random;
C=$random;

#600 A=$random;
B=$random;
C=$random;
end 
endmodule

And i have the errors :
# ** Error: D:/TEST/Er1v1SetAskLD.v(11): near "[": expecting: IDENT
# ** Error: D:/TEST/Er1v1SetAskLD.v(11): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(12): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(12): near ";": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(13): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(13): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(14): near "[": expecting: IDENT
# ** Error: D:/TEST/Er1v1SetAskLD.v(14): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(15): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(15): near ";": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(16): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(16): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(17): near "[": expecting: IDENT
# ** Error: D:/TEST/Er1v1SetAskLD.v(17): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(18): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(18): near ";": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(19): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(19): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(20): near "[": expecting: IDENT
# ** Error: D:/TEST/Er1v1SetAskLD.v(20): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(21): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(21): near ";": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(22): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(22): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(23): near "[": expecting: IDENT
# ** Error: D:/TEST/Er1v1SetAskLD.v(23): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(24): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(24): near ";": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(25): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(25): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(26): near "[": expecting: IDENT
# ** Error: D:/TEST/Er1v1SetAskLD.v(26): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(27): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(27): near ";": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(28): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(28): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(29): near "[": expecting: IDENT
# ** Error: D:/TEST/Er1v1SetAskLD.v(29): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(30): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(30): near ";": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(31): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(31): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(32): near "[": expecting: IDENT
# ** Error: D:/TEST/Er1v1SetAskLD.v(32): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(33): near "]": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(33): near ";": syntax error
# ** Error: D:/TEST/Er1v1SetAskLD.v(34): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(34): near "|": expecting: ',' ';'
# ** Error: D:/TEST/Er1v1SetAskLD.v(35): near "=": expecting: IDENT
# ** Error: D:/TEST/Er1v1SetAskLD.v(35): near "]": syntax error


Can someone Help me solve them?
 

Hi,

Put assign in front of all your assignment statements...

Combinational logic is implemented in verilog using either assign statement or always block.

Also, your code is redundant...(assign O = M ^ Y is enough)

What is the use of Verilog then?

Thanks,
Manoj
 
Oh yea what a childish mistake.....I added assign everywhere though just to be sure...
Hope someday they will let us do what i described above with actual chips :d
Thanks a lot for the help
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top