How to code the sdc for the generate clock below ?

Hi all.

I have a below schematic:



there are two clocks named clk1 and clk2. Then they are selected by a mux, then the output clock is divided by a two divided register.

Then the output of the register is used as the main clock for the following logic.

Also, there are some logic feeded by clk1 and clk2.

So could you tell me how to code the sdc for this scenario ?

Thanks all!

I will declare three asynchronous clocks.
1-clk1
2-clk2
3- the output of the two divided register
the open point is, do you have some logic between clk1 or clk2 to two-divided register output? Are they considere as asynchronous domains?

i need a process which will give me the complete description of the electronics to go forture in electric feild

You wrote for who ?

I may only select the fastest clock from clk1 and clk2, define it as the source clock for your divided-by-2 clock. The generated clock should be defined at the output of the flipflop. In the meantime, set constant value on the mux to propagate the fastest clock.

owen_li said:

Hi all.

I have a below schematic:

there are two clocks named clk1 and clk2. Then they are selected by a mux, then the output clock is divided by a two divided register.

Then the output of the register is used as the main clock for the following logic.

Also, there are some logic feeded by clk1 and clk2.

So could you tell me how to code the sdc for this scenario ?

Thanks all!

Click to expand...

owen_li said:

Hi all.

I have a below schematic:

there are two clocks named clk1 and clk2. Then they are selected by a mux, then the output clock is divided by a two divided register.

Then the output of the register is used as the main clock for the following logic.

Also, there are some logic feeded by clk1 and clk2.

So could you tell me how to code the sdc for this scenario ?

Thanks all!

Click to expand...

First create the two clocks by create_clock command.
set false path between clk1 and clk2
create generated clock as u are dividing it by 2 there is a direct command for that create_generated_clock.

Hi all!
How define multiplexing result clock before trigger?
Should I use set_case_analysis?

I second with nisshith's opinion . First create CLK1 and CLK2 definition by create_clock and then create one more clock at output of the register by using create_generated_clock

create_clock -name CLK1 -port CLK1 -waveform {0 5} -period 10
create_clock -name CLK2 -port CLK2 -waveform {0 10} -period 20

create_generated_clock -name CLKA -source CLK1 -div_by 2 div_by_2_reg/Q
create_generated_clock -name CLKB -source CLK2 -div_by 2 div_by_2_reg/Q -add

If output of the register be the main clock and clock generation starts from register output and goes to all leaf registers clock input then no need to specify relationship between CLK1 and CLK2.

If CLK1 and CLK2 still existing in the design then need to provide relationship between those two clocks.Like

set_false_path -from CLK1 -to CLK2
set_false_path -from CLK2 -to CLK1

I think by default tool considers all clocks are synchronous in nature.

Hi bschaitanya,
Can you please clarify the following SDC command?

"create_generated_clock -name CLKB -source CLK2 -div_by 2 div_by_2_reg/Q -add"

Why "-add" is used in the above command?

Rgds,
Kumar

Hi Kumar,

bschaitanya is correct but still I want to add few more points.

first of all - clk1 and clk2 are exclusive to each other. so you have to set a clock group with respect to these 2 clocks. For setting the exclusive clock you can use any of the option.

set_false_path -from CLK1 -to CLK2
set_false_path -from CLK2 -to CLK1

OR

set_clock_groups -logically_exclusive -group {CLK1} -group {CLK2}

you can also use the case analysis in case you want to disable a particular clock for any of your operation.

you can use the physically_exclusive option also in case there is not past relationship between the CLK1 and CLK2.. physically exclusive means no crosstalk between these clocks.

now for the divide by 2 clock .. you cn use following command- which is well know...

create_generated_clock -name DIVIDE_clock -source [get_ports CLK] -divide_by 2 [get_pins divide_by_2_reg/Q]

now the main question is how to generate or say name of the clock at port CLK of flipflop/register because after multiplexing the name of clocks are different.. for that purpose this -add option is used. See the snap shot of the -add switch in the create_clock

-add
Specifies whether to add this clock to the existing clock or to overwrite it. Use this option to capture the case where multiple clocks must be specified on the same source for simultaneous analysis with different clock waveforms. When you specify this option, you must also use the -name option.

if you are using the case analysis .... then there is no need of using this..

I hope this will help you.

@Birdy
Thanks for putting additional info especially physically_exclusive switch. It's a good way to define constraint with "set_clock_groups"

@ Kumar

Birdy provides info on " -add " switch

Here is an explanation why "-add" added..

That is, during timing analysis, CLK2 is never seen after the div_by_2 register.
During clock tree synthesis, only CLK1 is balanced through the MUX and the div_by_2_reg and CLK2 stop at the same register and treat it as a
SYNC pin. If you want CLK2 to trace through the div_by_2_reg, so we need to add the following additional generated clock:

"create_generated_clock -name CLKB -div_by 2 -pin core/div_by_2_reg/Q -source CLK2 -add"


-krishna chaitanya