[SOLVED] Verilog Back-Annotation from SoC Encounter to NCSim Using $sdf_annotate

I've read numerous similar threads but I still can't get this thing to work.

The Verilog design is a DFF with asynchronous R and S (dff.v). I have created a testbench in order to simulate the DFF in ncsim (dff_testfixture.v). I would like to back annotate the testbench file (dff_testfixture.v) with the timing data (dff.sdf) extracted from the routed design (dff.v) using SoC Encounter.

When I elaborate the testbench I get these warnings:

nclaunch> ncelab -work dff_test -cdslib /home/travis/dff_test/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status dff_test.dff_testfixture
ncelab: 06.20-s004: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
Reading SDF file from location "/home/travis/dff_test/dff.sdf"
ncsdfc: Memory Usage - 3.7M program + 2.3M data = 6.1M total
ncsdfc: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 100.0% cpu)
ncelab: *W,SDFCTE: Module dff_testfixture of instance dff_testfixture doesn't match SDF celltype of dff, skipping annotation <./dff.sdf, line 16>.
ncelab: *W,SDFANS: Attempt to annotate to non-existent source port S at scope level <./dff.sdf, line 19>.
ncelab: *W,SDFINF: Instance p214748365A26 not found at scope level <top-level> <./dff.sdf, line 24>.
ncelab: *W,SDFANS: Attempt to annotate to non-existent source port R at scope level <./dff.sdf, line 20>.
ncelab: *W,SDFINF: Instance p214748365A27 not found at scope level <top-level> <./dff.sdf, line 23>.
ncelab: *W,SDFANS: Attempt to annotate to non-existent source port D at scope level <./dff.sdf, line 21>.
ncelab: *W,SDFINF: Instance Q_reg not found at scope level <top-level> <./dff.sdf, line 26>.
ncelab: *W,SDFANS: Attempt to annotate to non-existent source port C at scope level <./dff.sdf, line 22>.
ncelab: *W,SDFINF: Instance p214748365A not found at scope level <top-level> <./dff.sdf, line 27>.
ncelab: *W,SDFAND: Attempted INTERCONNECT annotation to non-existent destination port nQ at scope level <./dff.sdf, line 26>.
ncelab: *W,SDFAND: Attempted INTERCONNECT annotation to non-existent destination port Q at scope level <./dff.sdf, line 27>.
ncelab: *W,SDFINF: Instance p214748365A27 not found at scope level <top-level> <./dff.sdf, line 33>.
ncelab: *W,SDFINF: Instance p214748365A26 not found at scope level <top-level> <./dff.sdf, line 42>.
ncelab: *W,SDFINF: Instance Q_reg not found at scope level <top-level> <./dff.sdf, line 51>.
ncelab: *W,SDFINF: Instance p214748365A not found at scope level <top-level> <./dff.sdf, line 68>.
ncelab: Memory Usage - 16.8M program + 12.0M data = 28.7M total
ncelab: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 76.4% cpu)
ncelab: ANNOTATION Time - 0.0s

After simulating the testbench it is clear that the sdf has not been taken into account (but you probably knew that much from the above warnings). The simulation runs exactly as it is supposed to, but changes at the output occur instantaneously with changes from the input, meaning 0 delay.

What is the problem? Why isn't the back annotation occurring after using $sdf_annotate? I noticed that the sdf contains definitions for nodes that weren't declared in the original design, but were automatically created in Encounter. Is that a problem?

I have tried so many different things after hours and hours and I'm about to lose my mind. Please, somebody definitively tell me what is wrong with my approach. Attached are the three files mentioned before.

View attachment dff_test.tar

I think it can be for one of the following reasons:

1. Do you use back-annotated netlist from SoC for simulation? You should use following simulations:
- RTL
- FrontEnd netlist
- BackEnd netlist + Back-annotation netlist

2. Do you use correct hierarchy with $sdf_annotate command?

3. Does your library cell DFF have "specify" constructs?

Kornukhin you are most wise. I think I actually have all three problems, but I have solved 2 and 3. I need your help in explaining 1 a little more. Here is what I have done:
-Added specify constructs to RTL netlist
-Corrected $sdf_annotate directive

To extract the netlist from SoC I did the following:
Design -> Save -> Netlist
And from that menu I can produce a netlist with the intermediate cell definition, leaf cell definition or both. But this can only produce a backend netlist, right? What is this frontend netlist you speak of? And how do I use the "BackEnd netlist + Back-annotation netlist" as you say?


When I elaborate the testbench with the new RTL netlist containing the specify constructs I get these warnings:

ncelab: *W,SDFINF: Instance p214748365A26 not found at scope level <top-level> <./dff.sdf, line 24>.
ncelab: *W,SDFINF: Instance p214748365A27 not found at scope level <top-level> <./dff.sdf, line 23>.
ncelab: *W,SDFINF: Instance Q_reg_reg not found at scope level <top-level> <./dff.sdf, line 26>.
ncelab: *W,SDFINF: Instance p214748365A not found at scope level <top-level> <./dff.sdf, line 27>.
ncelab: *W,SDFINF: Instance p214748365A27 not found at scope level <top-level> <./dff.sdf, line 33>.
ncelab: *W,SDFINF: Instance p214748365A26 not found at scope level <top-level> <./dff.sdf, line 42>.
ncelab: *W,SDFINF: Instance Q_reg_reg not found at scope level <top-level> <./dff.sdf, line 51>.
ncelab: *W,SDFINF: Instance p214748365A not found at scope level <top-level> <./dff.sdf, line 68>.


These warning are generated because the sdf refers to instances that were automatically generated by SoC, but are not in the RTL netlist. However, when I elaborate the testbench with one of the SoC extracted netlists I get these warnings:

ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH in out) of instance dff_testfixture.test.p214748365A27 of module inv <./dff.sdf, line 36>.
ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH in out) of instance dff_testfixture.test.p214748365A26 of module inv <./dff.sdf, line 45>.
ncelab: *W,SDFNSB: Attempt to annotate specify block data of instance dff_testfixture.test.Q_reg_reg of module dffSRaD, which has no specify block <./dff.sdf, line 53>.
ncelab: *W,SDFNSB: Attempt to annotate specify block data of instance dff_testfixture.test.Q_reg_reg of module dffSRaD, which has no specify block <./dff.sdf, line 54>.
ncelab: *W,SDFNSB: Attempt to annotate specify block data of instance dff_testfixture.test.Q_reg_reg of module dffSRaD, which has no specify block <./dff.sdf, line 55>.
ncelab: *W,SDFNSB: Attempt to annotate specify block data of instance dff_testfixture.test.Q_reg_reg of module dffSRaD, which has no specify block <./dff.sdf, line 56>.
ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH (posedge C) nQ) of instance dff_testfixture.test.Q_reg_reg of module dffSRaD <./dff.sdf, line 60>.
ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH R nQ) of instance dff_testfixture.test.Q_reg_reg of module dffSRaD <./dff.sdf, line 61>.
ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH S nQ) of instance dff_testfixture.test.Q_reg_reg of module dffSRaD <./dff.sdf, line 62>.
ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH in out) of instance dff_testfixture.test.p214748365A of module inv <./dff.sdf, line 71>.

Neither case simulates with the correct delays.

trav1s said:

To extract the netlist from SoC I did the following:
Design -> Save -> Netlist
And from that menu I can produce a netlist with the intermediate cell definition, leaf cell definition or both. But this can only produce a backend netlist, right? What is this frontend netlist you speak of? And how do I use the "BackEnd netlist + Back-annotation netlist" as you say?

Click to expand...

FrontEnd netlist is a netlist from logic synthesize tool (like RTL compiler or Design Compiler). BackEnd netlist is a netlist from layout tool (SoC Encounter).
Both BackEnd netlist and Back-annotation SDF (not netlist as I wrote) you can get from Encounter.

Then you need to do following:
- compile leaf cells (with specify blocks)
- compile BackEnd netlist (without leaf cells)
- elaborate testbench with $sdf_annotate

warnings like this:
"ncelab: *W,SDFINF: Instance p214748365A26 not found at scope level <top-level> <./dff.sdf, line 24>."
shouldn't appear because netlist must match SDF (both from the same tool).

warning
"ncelab: *W,SDFNSB: Attempt to annotate specify block data of instance dff_testfixture.test.Q_reg_reg of module dffSRaD, which has no specify block <./dff.sdf, line 56>."
said that module dffSRaD doesn't have specify block

warning
"ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH in out) of instance dff_testfixture.test.p214748365A27 of module inv <./dff.sdf, line 36>."
said that your specify block is incomplete (no delay from "in" to "out")

After changes it should works fine.

Based on your comment I adopted a more standard design flow and it has exposed more problems. Namely, I have realized that at RTL compilation additional logic is unnecessarily being created. For now I must postpone following your suggestions until I find why RTL compiler is not producing optimal designs. I have posted a full description of my problem here:
https://www.edaboard.com/threads/198784/

Re: VHDL Back-Annotation from SoC Encounter to NCSim Using $sdf_annotate

Hi all

I am facing similar problem during back-annotation

I am using Design compiler to generate the vhdl gate level netlist and also SDF file. I follwed the below mentioned commands for back annotaion

1. compiled the sdf file using
ncsdfc addr_gen.sdf
--this created a .X file
2. elaborated using
ncelab -work worklib -sdf_cmd_file addr_gen.sdf_cmd -cdslib /home/achundur/address_generator/post_syn/Back_annotate/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status worklib.addgen_tb:entity

-- where the addr_gen.sdf_cmd is a file containing the follwing commands
COMPILED_SDF_FILE = “addr_gen.sdf.X”,
SCOPE = :UUT,
MTM_CONTROL = "TYPICAL",
SCALE_FACTORS = "1.0:1.0:1.0",
SCALE_TYPE = "FROM_MTM";
--During elaboration process I am getting following warnings

DEFINE ieee ./IEEE
|
ncelab: *W,SDFCONV (/usr/local/cadence/IUS0810019/tools.lnx86/inca/files/cdsvhdl.lib,3): Converted illegal VHDL element "l_reg_reg\[14\]" into legal VHDL name "l_reg_reg[14]".
.
.
similar warnings for all bits
.
ncelab: *W,SDFINF: Instance base_reg_reg[14] not found at scope level addrGenerator_1 <./addrGen_unit.sdf, line 33061>.
.
.
similar warnings for all bits
ncelab: Memory Usage - 18.0M program + 23.9M data = 41.9M total
ncelab: CPU Usage - 0.1s system + 0.8s user = 0.9s total (1.0s, 92.2% cpu)
ncelab: ANNOTATION Time - 0.3s

I ignored the warnings of second type because my generated sdf file is with zero interconnected delay model and at the specified line in warnings of second type I am having interconnect delays( all 0's) in sdf file
And finally it is showing annotation time =0.3 ns . but when I observe in waveform window I am not able to see any delays annotated . the simulation is exacltly with zero delay..
please help me in resolving this. Am I missing some thing?

Before writing netlist try perform next command:
change_names -rules vhdl -hierarchy

Hi poluekt:

Thanks for your help. I tried your suggestion and resolved the above warnings. I have another issue , eventhough I am using following command in my synthesis script
sdfout_no_edge = true
still It is showing the SDFGENNF warnings and Simulation is showing without delays
ncelab: *W,SDFGENNF: Generic "TPD_CDN_Q_OP_OP_CP_EQ_1_CP_AN_OP_D_EQ_0_CP_CP_AN_OP_E_EQ_1_CP_negedge" not found in component ":addGen_tb:U1:addrGenerator_3:m_reg_regx3x:" <./addrGen_unit.sdf, line 10126>.

And Is above warning preventing me to see the simulation with delays annotated on it ? Please help with this

I can't find variable "sdfout_no_edge" in sold documents (2010.3). Why do you decide to use this variable?

Hi poluekt:

I got this one of the threads. Please let me know if there any other way..

the reason was given in that thread as follows

--the latest Synopsys DC version has been enhanced for edge relativetiming and now most of the vital library are not compatible with the new SDF generated by DC. In order to solve this problem end to get a DC 98.08 like SDF you can set in your .synopsys_dc.setup a variable call
sdfout_no_edge = "true";

please see the following link also
**broken link removed**
https://www.edaboard.com/threads/220499/