[SOLVED] Problem with Common Centroid Mixing

Hi, i'm learning how to draw layouts using IC Station from Mentor Graphics. I'm having a problem running the LVS for the circuit and am beggining to think that i have mixed some of the transistors in an incorrect manner. What would be an ideal way of mixing 4 NMOS transistors with the same widths and lengths that share a common gate but not source nor drain, so that they have an exact or at least approximate common centroid?


Currently i have them in the following configuration: Gd S1 G D1 Gd S2 G D2 Gd S3 G D3 Gd S4 G D4 Gd D4 G S4 Gd D3 G S3 Gd D2 G S2 Gd D1 G S1 Gd , where Gd denotes the dummy gates i used and connected to ground (should i leave them floating?), these transistors are supposed to be part of a current mirror so current matching between them is very important .

Any help is greatly appreciated. I'm currently stumped.

pedrogush said:

... share a common gate but not source nor drain
Gd S1 G D1 Gd S2 G D2 Gd S3 G D3 Gd S4 G D4 Gd D4 G S4 Gd D3 G S3 Gd D2 G S2 Gd D1 G S1 Gd

Click to expand...

All the bold-represented sources & drains are shared.

So is there a way to use dummy gates so i can mix these NMOS or is it just not possible? Do i necessarily have to draw each of them individually?

pedrogush said:

So is there a way to use dummy gates so i can mix these NMOS or is it just not possible? Do i necessarily have to draw each of them individually?

Click to expand...

Please specify the details of transistors, like how many transistors needs to be matched and no: of fingers of each transistor.

pedrogush said:

So is there a way to use dummy gates so i can mix these NMOS or is it just not possible? Do i necessarily have to draw each of them individually?

Click to expand...

If you don't want to share any sources or drains, each transistor has to have its own source and drain next to its gate in their own active area.

If you don't want to share any sources or drains, each transistor has to have its own source and drain next to its gate in their own active area.

Click to expand...

Thanks, i ended up drawing them each individually and placing them on minimum distance next each other for the moment, since i'm just trying to learn how to make things work.

Please specify the details of transistors, like how many transistors needs to be matched and no: of fingers of each transistor.

Click to expand...

I have 4 NMOS transistors with a width of 68 lambda and a lenght of 3 lambda, their gates are shared but they don't have drains or sources in common, these are part of a cascoded current mirror so i had to match them as precisely as possible. Ideally i'd like them to have a common centroid so at least 2 fingers for each drain and source so at least 16 fingers. My initial thought was that placing a dummy gate in the middle of a contact and connecting it to ground would let me work with the transistors behaving in a semi-independent manner since the the dummy gates would have no channel/ be turned off, and in this way i would be able to do something like: dummy 1 dummy 2 dummy 3 dummy 4 dummy 4 dummy 3 dummy 2 dummy 1 dummy. I'm thinking i made a mistake here since i tried the options on LVS in order to make it recognize dummy gates and ignore them.

Hi pedrogush,

I found two solutions for mixing of transistors in a shared diffusion.

1. If the cell is area tight. Then d A B C D D C B A d would work with individual active areas. d-Dummy and A B C D are gates.
2. If it is area free and requires precise matching then "d A d d B d d c d d D d d D d d C d d B d d A d" would work with a common shared diffusion.
But In this case, I would take the connections like below. And also I would connect the Dummies gates to GND to turn-off.

GND d Drain of A A Source of A d VSS d Drain of B B Source of B d

Hope this would help your query.

Regards,
Siva Prasad.

Hi pedrogush,

I found two solutions for mixing of transistors in a shared diffusion.

1. If the cell is area tight. Then d A B C D D C B A d would work with individual active areas. d-Dummy and A B C D are gates.
2. If it is area free and requires precise matching then "d A d d B d d c d d D d d D d d C d d B d d A d" would work with a common shared diffusion.
But In this case, I would take the connections like below. And also I would connect the Dummies gates to GND to turn-off.

GND d Drain of A A Source of A d VSS d Drain of B B Source of B d

Hope this would help your query.

Regards,
Siva Prasad.

Click to expand...

Thanks! I will try this at friday the latest, unfortunately i have to redo a lot of routing to make that work, but i am much obliged.

sivaprasad1324 said:

Hi pedrogush,

I found two solutions for mixing of transistors in a shared diffusion.

1. If the cell is area tight. Then d A B C D D C B A d would work with individual active areas. d-Dummy and A B C D are gates.
2. If it is area free and requires precise matching then "d A d d B d d c d d D d d D d d C d d B d d A d" would work with a common shared diffusion.
But In this case, I would take the connections like below. And also I would connect the Dummies gates to GND to turn-off.

GND d Drain of A A Source of A d VSS d Drain of B B Source of B d

Hope this would help your query.

Regards,
Siva Prasad.

Click to expand...

you can use this, but if you want a common centroid matching you can use the following matching pattern

d A B D C d
d C D B A d

Thanks & Regards
Sreehari