ivlsi
Advanced Member level 3
Hello All,
As for the SDF file, which designers get from the Layout team and run STA checks on their modules, is it a common for all the chip. I mean, should each designer take a big SDF file for the whole chip for just running STA checks on its small module?
Could the full-chip SDF be divided to the smaller parts, so each designer will back annotate only gates and nets from the module on which he/she run STA checks?
Hopefully you got my point...
Thank you!
As for the SDF file, which designers get from the Layout team and run STA checks on their modules, is it a common for all the chip. I mean, should each designer take a big SDF file for the whole chip for just running STA checks on its small module?
Could the full-chip SDF be divided to the smaller parts, so each designer will back annotate only gates and nets from the module on which he/she run STA checks?
Hopefully you got my point...
Thank you!