Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Can a buffer speed up a path

Status
Not open for further replies.
B

beowulf

Member level 4
Member level 4
Joined
Jan 19, 2005
Messages
69
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
581
Hi,
I have a simple connection between points A and B. Lets say it has some delay 'd' due to wire resistance.
Now, can we put a buffer between A and B such that the delay can be reduced.

Thanks,
Beo
 

Yes you can in my opinion. This is referred to as registering a signal. The timing only needs to be considered before and after the buffer individually. The propagation delay will be lower as the buffer "splits the timing path".

The propagation delay portion however is typically lower than the logic delay so doing this may not make as much of a difference as you would think.
 
Depends on length, capacitive load, operation frequency and the capacitance that is driven by the block before buffer. Most of the time if you require this type of improvement in normal circuit, it means that it cannot be automated so try other solutions. But in special designs like ALU's it is used to optimize every delay. In any case best way to cope with delays in metal lines is to get them closer.
 
  • Like
Reactions: rreddy

    R

    rreddy

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top