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[Synthesis] How black-boxes should be handled during the synthesis?

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ivlsi

ivlsi

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How should be handled black boxes in the RTL during the synthesis? Let's say I have a Black Box in my Netlist, which represents an analog module. There are requirements on the timing for its inputs and outputs. How should I implement this timing in the synthesis/sta scripts? Again, this block box is inside another code and does not have its own ports in the top-level.
 

The easiest way is to create (manually or by using special software) the timing model of such block with all needed requirements. Timing model - it's a synopsys .linb file (as example). Special software - it's a characterization tool (Synopsys Liberty NCX) (it may be difficult to run it on the analog block).

Then, you may use this timing model (.lib) in the same manner as you are using other .lib files (of std. cells). In DesignCompiler you should add this .lib in the link_library.
 
Ok, I've got your point, thank you!
 

Primetime propose the quick time model.

---------- Post added at 17:40 ---------- Previous post was at 17:39 ----------

To generate .lib view based on the current liberty std cell view.
 
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    ivlsi

    ivlsi

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cell view
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What does it mean - cell view? Could you please elaborate?
Thank you!
 

you load in primetime the current std cell liberty to have the timing of the pvt you want modelize your macro.
 

std cell liberty
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cell liberty or library? is it a typo or a term? could u give an example how this "liberty" looks like? Is this a text file?
 

Liberty file is the .lib file, also compile with library compiler form Synopsys in.db file.
 
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    ivlsi

    ivlsi

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Thank you! Now I know that the "liberty" is a full name for the .lib files :)
 

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