Layout of gain boosted op amp!

hi friends,
i am trying to do the layout of gain boosted op amp for use in my pipelined ADC. It is a fully differential one with two auxiliary op amps one with NMOS input pair and the other with PMOS input pair. The schematic results of the op amp are good and i started the layout. The problem i am facing in the layout is after i do the post layout simulation i see a large difference in the voltages between the two output nodes. The reason for this is also evident. Since gain boosting op amps are of very high gain, the output impedance will be very high. So, in a folded cascode implementation , even a 1uA mismatch between the two stacks of the cascode may result in large difference between the output nodes. But how to solve this problem? I have been working really hard to solve this issue but somehow a little mismatch (somewhere in the mirrors or the common centroid layouts or the auxiliary op amps) is inevitable. Also i observe different swings on the two output nodes in the post layout simulation. What could be the reason for it?please help me with this layout guys.....awaiting replies......

i think it is quite normal. You have to minimize the offset, but it is impossible to cancel it out at all. i think that you have to ensure that systematic offset is lower than mismatch offset. I think you have to ensure that your output do not saturate. however, when the amplifier is closed in a loop, the output will be fixed by the feedback,no matter of offset, which will be present at the input.

Actually the CMFB circuit i am using is a switched capacitor based one....but my question is CMFB takes care of the output node voltages if either both rise or both fall i.e., common mode...but if one node rises and the other falls then how will the CMFB help?....please help me understand....are there any special techniques for layout of gain boosted opamps?

sorry my first answer was misunderstood

---------- Post added at 20:25 ---------- Previous post was at 20:24 ----------

you can also consider that mismatch in your design will give you the same effect. I think it is not a major concern, how much your output difference is, when your amp is open loop.

are you saying that the offset will be eliminated when the op amp is placed in closed loop feedback configuration , no matter how large the offset is?

---------- Post added at 00:59 ---------- Previous post was at 00:57 ----------

thanks for your reply....let me check it......

---------- Post added at 01:18 ---------- Previous post was at 00:59 ----------

ok please tell me why there is unequal swing at the output nodes for the same input signal?

mismatch and non simmetry in your layout. the offset won't be eliminated but the output won't saturate thanks to negative feedback. your offset will be present as a difference between inputs, i.e. non ideality in applying virtual short circuit.

I tried with CMFB circuit also....the result is the same.......
yeah it won't be a problem in negative feedback configuration but the problem i have to show, in my thesis, comparison between schematic and post layout AC simulation results . Because of this non ideality the output voltages are very different and some transistors are going into linear region because of which i see a large reduction in the open loop gain. Please tell me how to solve this...

I don't know the DC gain openloop gain of your boosted. -but it is, let's say, 120 dB, which is a poor gain, the output saturates with 1.5 uV unbalance at the input. you have to take into account that also mismatch on the mosfets, that post layout does not take into account, will give the same effect.

one idea is:
do a DC sweep of the differential input voltage until you see that the output is 0. then, this is your offset voltage. then, simulate the op amp biasing it with the offset at the input. you should observe the right output gain. it is the same that biasing with 0 DC and 1 AC in the ideal case.

let me know if it goes ok!

I have tried that also but strangely the two outputs are never reaching the desired output voltage(900mV). There is no convergence. Ok let me check it again...

maybe you have to perform a sweep in a very small range with a very small step, due to the very large gain. try it.

Sir,
i am very glad. It was a great help. Thanks a lot. your idea of DC sweeping in a very small range worked. thanks once again....

can you let me know how much your input offset is? just a curiosity ^^

it is around 1.2mV.......it is very high but the convergence occured only at that offset.....i dont know why......it is not matching with the theoretical calculations.....but the convergence occured only when i did the DC sweep in a very small range.....anyway my job is done....
thanks once again...

yes it is high if no mismatch in the mos is present. no problem. bye