Getting problem with CCD check due to use of "generate" block in one design file

Getting problem with CCD check due to use of "generate" block in one design file

Hello all,

I am currently running a CCD check using Cadence Encounter(R) RTL Compiler for an IP which consists several *.v files.

In one of the .v files the "generate" statement has been used -- This is causing an error while I run my CCD script.

-----------------
Error msg given by compiler:

// Parsing file ~hdl/abc.v ...
// Error: hdl_default_checks/rtl_checks/RTL13.6: Standalone generated blocks are not supported in the IEEE standard
// In line 235, file '~hdl/abc.v'
// Error: Fail to read design.
// Read design summary: Error: 1, Warning: 0, Note: 0
-----------------

CCD script which reads the design file:

read design -verilog2k -define <company_tech_name>\
-root <....> \
-parameter <...> \
hdl/some_file.v \
hdl/abc.v \
hdl/some_file.v \
-lastmod -noelab

-------------------------

So can anyone please tell me what options I must use so that the error message regarding use of "generate"
statement in design dosen't show up?

Hope I am clear in the explanation!

Thanks & Regards,
dpaul

---------- Post added at 12:02 ---------- Previous post was at 11:56 ----------

The part of the code in the design file where this "generate" statement is used......

// ----------------------------------------------------------------------------
// Generate statement to connect memory banks attributes to read/write banks of
// memory controller.
// ----------------------------------------------------------------------------
generate
begin
for(i=32'd0; i<SRAM_IF_NO_OF_BANKS; i=i+32'd1)
begin : memory_bank
assign sram_wdata_int[(i+32'd1)*78-32'd1:i*78] = b_wdata;
assign sram_addr_int[(i+32'd1)*
SRAM_IF_BANK_ADDR_WIDTH-32'd1
:i*SRAM_IF_BANK_ADDR_WIDTH] = b_addr;
assign sram_dm_int[(i+32'd1)*78-32'd1:i*78] = b_dm;
assign sram_ce_int = ce;
assign sram_we_int = we;
assign b_rdata = iSRAM_RDATA[(i+32'd1)*78-32'd1:i*78];
end
end
endgenerate

Re: Getting problem with CCD check due to use of "generate" block in one design file

Any help on what should be the switch to avoid the message given above for the command :

"read design"

I have checked through Cadence documentation....did not find any!

Re: Getting problem with CCD check due to use of "generate" block in one design file

can you try the command "set rule handling " and change that to warning...