Parameterized demultiplexer in verilog

Hi,

I am trying to design a parameterized 1-to-N demultiplexer in Verilog but couldn't come up with proper code for it. I know how to design a dmux but am having trouble with making it parameterized. It would be great if someone could help me out with it.

Thanks
Sid

I have 2 questions from the above code,if u dont mind answering (iam not saying the code is wrong )

1. what difference would it make if i put an always block instead of generate


2. if i synthesize the above code , will "clog2" be synthesized ?...if not, then why and in which cases does it not synthesize?

Thanks,
in advance

1. no difference
2. function clog2 is synthesizable.

Thanks for the reply,
Is there a way i can assign a value to local parameter as clog2(N) (during compilation) without actually synthesizing it?
bcoz its just a parameter, why synthesize something to assign a value to it?

this function doesn't generate physical logic and is used for local parameter calculation. "synthesizable" in my interpretation - support by synthesis tools.

clogb2 function does not actually synthesize to any actual hardware. Its just a constant function used in order to calculate the complex parameterized values.

During synthesis process, on of the very initial tasks the tool performs is code related processing, i.e. calculation of constants, syntax check, low-effort compile, loop unrolling, subprograms (tasks and functions) expansion, dead code removal, etc. and this is where it actually calculates the value of the parameter through the clogb2 function before performing further RTL level, logic level and gate level synthesis/optimization performing.

In short, you are not inferring any hardware, but just defining the constants in a bit complex way.

---------- Post added at 09:08 ---------- Previous post was at 08:57 ----------

manojkhandelwal said:

I have 2 questions from the above code,if u dont mind answering (iam not saying the code is wrong )

1. what difference would it make if i put an always block instead of generate

Code:

integer i;
always@(in,sel)
begin
for(i=0;i<N;i=i+1)
out[i]= (sel==i )? in :1'b0;
end

2. if i synthesize the above code , will "clog2" be synthesized ?...if not, then why and in which cases does it not synthesize?

Thanks,
in advance

Click to expand...

Yes you can use always statement.

Here's the dmux code that I came up with, it doesnt use clogb2 or generate statements, instead uses a shift operation for constant calculation and a simple always statement

module dmux
#(parameter WIDTH = 4)
(input in,
input [WIDTH-1:0] addr,
output reg [(1<<WIDTH)-1:0] out
);

always @*
begin
out = 0;
out[addr] = in;
end

endmodule

Thanks for your help

Well thanks a lot.....that clears the doubts in my mind.