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[Layout] Clock Tree routing

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ivlsi

ivlsi

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Hello All,

Should the clock tree be routed in the different layers than other logic signals?

Should the high fanout signals be routed in the different layers than other logic signals?

Thank you!
 

Yes, they give especially very special care for clock trees.

The thicker metal lines do not have a speed advantage in most of the digital processes but in order to keep the longest line of clock at minimum impedance, clocking network generally is thicker. There should be many more good practices about clocking network, I honestly do not know much about digital layout design. If there are more experienced engineers around they could give you more hints and tips.

Other than very special signal lines like clock, most of the time only optimization alternative is to get them closer.
 

Preferably clocks must be routed in the top layers. Consider a 7 layer design, M7 and M6 are for power, M5 and M4 is for clock. Although rest of the signals can also be routed in M5 and M4, clocks will be usually shielded and have higher width.
 
Clock tree is always given more preference than other signals in terms of routing because maximum switching takes place in these nets and clock needs to be propagated to all the cells. Thus, they need to have minimum IR drop and more current capacity. Thus top layers(just below power nets) are used for clock routing which have more current conductivity due to more thickness of metal layers at the top. Moreover clock nets have double thickness and double spacing between them with shielding. I don't know the reason for double thickness but double spacing is to prevent crosstalk.
 
Clocks are routed on Higher metal layers just below the top metal layers and they use non default layer routing for double width and spacing. Double width for reliability and dec resistance and double spacing for reducing crosstalk induced noise and delay.


For high fanout there is no such constraint given as per my knowledge.
 
@pavanks: I'm not a pro in vlsi domain. I'm myself in the learning phase. So I might go wrong at some places. But, if high fanout is not a constraint, then why top layer is being reserved for clocks because in my knowledge the only reason we use top layers is high current conductivity...Plz clarify!!
Thanks..
 

Is the Base Layer the thinnest and lowest one (located on the bottom of all layers)?

---------- Post added at 10:33 ---------- Previous post was at 10:31 ----------
Consider a 7 layer design, M7 and M6 are for power, M5 and M4 is for clock.
Click to expand...
Whats' about GND? Is it on the same layer as Power?

---------- Post added at 10:34 ---------- Previous post was at 10:33 ----------

Is the Base Layer the thinnest and lowest one (located on the bottom of all layers) ?
 

It is generally preferable that the lower layers are thin because the signal routes needn't withstand high current. Moreover if the layers are thick, than more spacing will be required according to minimum spacing rule. Thus lesser no. of metal tracks will be available for routing.

---------- Post added at 14:10 ---------- Previous post was at 14:09 ----------

I dont know about base layer though...i thought u were talking about lowest metal layer..:)
 
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    ivlsi

    ivlsi

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Do all the Metal Layers located above the layer where all the std cells and memories located?

What about location of the cells, which are manufactured in the different technologies (lets say some of them @90nm and others @120nm)? Should all of them be placed on the same layer, which has the same thickness?

Thank you!
 

Do all the Metal Layers located above the layer where all the std cells and memories located? - Yes. Sometimes, we block the routing (in metals) above critical cells (like memory bitcell).

What about location of the cells, which are manufactured in the different technologies (lets say some of them @90nm and others @120nm)? Should all of them be placed on the same layer, which has the same thickness? - The cells developed in the different technologies should be placed on different chips. Or, I have misunderstood your question?
 
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    ivlsi

    ivlsi

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Or, I have misunderstood your question?
Click to expand...
No, actually you answered the question, which I asked...
But, there is something strange on my side... The vendor, which we work with, told us that the memories, which we are going to use, are developed for a different technology than std cells, which we are also going to use... But, these cells and memories are going to be placed on a single chip... Could you explain how is it?

As for the flip-chips, are they developed in order to place the dies, which were produced with different technologies, under the same chip package?

Thank you!
 

I have a doubt regarding layers. It is said that all the cells and macros lie on base layer. Now, by definition, macros are like black boxes and internally all the routing is already done in it. Now my question is how can a macro lie entirely on base layer when there is metal routing done inside?
Thanks.
 

dmitryl said:
No, actually you answered the question, which I asked...
But, there is something strange on my side... The vendor, which we work with, told us that the memories, which we are going to use, are developed for a different technology than std cells, which we are also going to use... But, these cells and memories are going to be placed on a single chip... Could you explain how is it?

As for the flip-chips, are they developed in order to place the dies, which were produced with different technologies, under the same chip package?

Thank you!
Click to expand...

Memories can be of diff technology as they are hard macros u dont synthesis it. U just place in on ur core and do the design.
If u remember during synthesis there are target lib and link lin concepts.
Target lib is the std cell lib to which ur design is assigned to excluding the macros.
Link lib are macro lib which are linked to ur design. So link lib can be of any tech.
 
Thank you pavanks! But my doubts are still present... How do the different technology cells (even hard macros) might be placed on the same layer... They have a different transistor sizes are not them? Or do all the transistors (not a matter what technology of they are) always have the same height (in order to keep the same uniform height/thickness of the layer)?
 

dmitryl said:
Thank you pavanks! But my doubts are still present... How do the different technology cells (even hard macros) might be placed on the same layer... They have a different transistor sizes are not them? Or do all the transistors (not a matter what technology of they are) always have the same height (in order to keep the same uniform height/thickness of the layer)?
Click to expand...

Why does it matter for a macro ?
For a macro u need is the outline of the macro. U dont synthesize it. U just use it in ur design. Right
 

As for the different technologies (let's say for 90nm and 250nm), will CMOS transistors have the same or different height (Gate and so on...) ? Thank you!
 

Surely they will have different height. Even the same channel length processes may have different height. But this is not a design variable since it is decided by the process guys. The thing you can do to reduce your height considerations is filler cells and dummy devices if that is what you are asking.
 

Okay, Thank you!
 

dmitryl said:
Is the Base Layer the thinnest and lowest one (located on the bottom of all layers)?

---------- Post added at 10:33 ---------- Previous post was at 10:31 ----------


Whats' about GND? Is it on the same layer as Power?

---------- Post added at 10:34 ---------- Previous post was at 10:33 ----------

Is the Base Layer the thinnest and lowest one (located on the bottom of all layers) ?
Click to expand...


Yes, usually when you have the power structure , the structure will have "power gnd pwr gnd" like alternating strips on the same metal.

Lower metals upto certain level M1 M2 M3 M4 will have same thickness and the metals above will have higher thickness.
 

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