Synthesis without inverters with RTL compiler

Hey all.

I am traying to synthesize a design with a custom made library without basic inverters. In general, RTL compiler requires inverters and some other basic cells. And so i recieve the following message: "synthesis failed- do not have usable inverters". I'm using cadence's RTL compiler.

My library have all the logical variety of cells except a straight forward inverter. Including: (A+B'), AB', A(BC)'...... and alot more options to create the logical function of an inverter out of them. Or to combine it with the approximate cells for one of the above functions.

From the aspect of logical variety, the synthesizer is theoreticlly able to creat any IC without a regular inverter. Can I somehow delete this requirement of having an inverter cell in my library? Or am i some-how hitting on some heuristics that suddenly are invalid with the absence of the inverter??

Thank you very much

HI...

I don't think that is possible in RTL Compiler i.e. synthesizing w/o any basic inverter. The ideology behind it is that to implement any logic basic gates of inv, and, or, buff etc are requried for which it looks for and crib's if not found.

For more details you may want tor ead this tread - https://www.edaboard.com/threads/240303/

Thanks for the answer.

Do someone knows if there is an alternative synthesizer which is capable of synthesis proccess without inverters? I have access to Synopsys' DC. Is it possible there? Xilinx's tool? or maybe freeware tools?

it would be always gr8 to give it a try.. there is no loss right. But i believe it would be the same case with DC as well.
I request you to pls share your observation here once concluded, will help me understand as well.

You have not found some design that is invalid without an inverter. NAND2 and NOR2 (and others) are functionally complete. Its just that inverters are a very basic building block of a library and designs may suffer heavy penalties without them. The lack of an inverter is and should be a warning sign that there is a severe problem with the standard cell library.

Solution 1:
Make a copy of your .lib file and edit it by setting the cost of one of the inverters prohibitively high. So make the timing really poor or the power really high, depending what RC is optimizing for. Then for the other inverters you didn't modify, just set those as don't use. RC will then likely choose a single NAND2 rather than an inverter when an inverter is necessary, because RC will think a NAND2 is lower cost.

Solution 2:
Simply make a inverter out of a NAND2 by connecting the two inputs together. Then place the definition of that in the .lib.

Solution 3:
There is a way to replace all instances of a standard cell with another standard cell using the command line interface. It is described in the section "Changing the Instance Library Cell" in the manual. However, this example is only for when the pin mappings are equal. It should be possible, however, to map the inverters input to both NAND2 inputs with a little creativity.

@trav1s

I am not sure if soln (1) would work cause from what i understood from the question is that there is no simple inverter. changing PPA cost would help choose the priority of a libcell that is being used by the tool; although here it is not used at all.

Also (3) if the mapping is done, but here the tool cribs and stop at the mapping stage itself.

I agree with (2) - if the library well modified and the function is well understood by the tool it should use it as an inverter.

I assumed he was starting with some sort of standard cell library. If thats not the case, its quite easy to make a dummy inverter definition in order to use solution 1 or 2.

from synthesis yes he can do that. But he will again be gated from progressing further at PnR stage as he will not have any physical info for this libcell.
I still think (2) is best if the tool understands the libcell and its function once modified.

else as we discussed before library should have an inverter

In Cadence SoC Encounter it is permissible to have a cell defined in the Liberty timing file, even though there is no physical information in the library if the cell is not used in the design netlist.

In theory, all three solutions will result in a post-synthesis netlist which contains no inverters.

Therefore, the physical information for the dummy libcell is unnecessary and place & route can progress.

Hey all. Thanks for all your ideas. I cannot write here all the technology details, but it is somewhat domino-logic like. Meaning, that each cell is actually constructed with 2 smaller cells. Therefore i can creat a nand-inv chain, but cannot inv itself as a lone cell. Regarding trav1s post, we have other logic alternatives in our library for the inverter and don't need to worry about our IC's delay and power consumption (which are much better than in standard CMOS technology).

Solution 1: We already tried it, putting an "infinite" delay and power to a dummy inverter cell in hope the the synthesizer will not use it. But in fact, some inverters are still remain after the synthesis proccess.

Solutions 2+3: As I mentioned before, an inverter implementation using nand2 with the legs connected is not possible in our technology, so it is not relevant.

If you still have some creative ideas, we would very like to hear them.
Thanks again...

I think the only way you have to resolve this is to add a "dummy" inverter to your library, so that this is accepted from the synthesis tool.
Then you put a "set_dont_use" on this cell, so it will not be inserted in you final design.

See if this works...

That doesn't work either, I just tried it. Setting a cell to don't use is just the same as not having in the library at all.

OhaAmo said:

Hey all. Thanks for all your ideas. I cannot write here all the technology details, but it is somewhat domino-logic like. Meaning, that each cell is actually constructed with 2 smaller cells. Therefore i can creat a nand-inv chain, but cannot inv itself as a lone cell. Regarding trav1s post, we have other logic alternatives in our library for the inverter and don't need to worry about our IC's delay and power consumption (which are much better than in standard CMOS technology).

Solution 1: We already tried it, putting an "infinite" delay and power to a dummy inverter cell in hope the the synthesizer will not use it. But in fact, some inverters are still remain after the synthesis proccess.

Solutions 2+3: As I mentioned before, an inverter implementation using nand2 with the legs connected is not possible in our technology, so it is not relevant.

If you still have some creative ideas, we would very like to hear them.
Thanks again...

Click to expand...

I'm sorry, I don't totally understand why using a nand2 as an inverter is not possible in your technology. Or you could use some other cell to serve the inverter funtion. You said (A+B') is available. All you would need to do is create a copy of that cell with the A term tied to logical low, then change the description in the .lib file so that the output pin function : "!B" ;. Technically it is still a (A+B') gate. What am I missing? Could you explain the problem a little more?

ohAmo

in case where you discuss abt your Solution (1) as below
--
Solution 1: We already tried it, putting an "infinite" delay and power to a dummy inverter cell in hope the the synthesizer will not use it. But in fact, some inverters are still remain after the synthesis proccess.
--

This is expected, hence the error dont you think.. i would have been surprised if there was no inverter finally. It is there that means that your design requires a normal inverter...
I would also like to understand if you can use a dummy inverter why cant you use an existing nand2 that is available in your libraray to act as inverter.
I think you need to agree that without inverter the mapping will not happen...

Did you get a chance to execute the same setup with DC.. does it ask for an inverter as well?

@trav1s
We have dynamic cells which are constructed from 2 following gates, the first link output is precharged to 1, while the second one is prechared to 0. Therefore, the total function of a cell in our technology requires low output with low input for the precharge. Because of that, a simple inverter is not supported, while functions like XOR, A'B and so on are. But, a simple inverter or gates like nand2/nor etc, can be implemented as one of the two cell gates (But must follow with another gate and not as a single gate).

@englishdogg
We are working on executing the same setup with DC, still not have any results in that direction.
Because of that our library does have a wide range of logic functions, we hope that we can map any design without any "simple inverter". As for the reasons why we cannot implement inv from nand2 see above. Actually nand2 is as well not a simple cell in our library, but it is a link in 2 gates cell.