ivlsi
Advanced Member level 3
Hello All,
According to the vendor's methodology, I should synthesize my design with two runs.
On the first run, I should use the Low-Vt cells only.
On the second run (if there are timing violations), I need to replace Low-Vt cells with High-Vt cells on the critical paths only (or vice versa, I don't remember . which one of them is faster?).
The tool, which I use, is RTL-Compiler from Cadence.
My question: how is it possible to replace cells just on critical paths and preserve cells on the rest of paths? What command should I use and how should I guide the tool to do so?
Thank you!
According to the vendor's methodology, I should synthesize my design with two runs.
On the first run, I should use the Low-Vt cells only.
On the second run (if there are timing violations), I need to replace Low-Vt cells with High-Vt cells on the critical paths only (or vice versa, I don't remember . which one of them is faster?).
The tool, which I use, is RTL-Compiler from Cadence.
My question: how is it possible to replace cells just on critical paths and preserve cells on the rest of paths? What command should I use and how should I guide the tool to do so?
Thank you!