ivlsi
Advanced Member level 3
Hello All,
What steps are usually used for fixing timing violations after first-run synthesis? Let's say that all the boundary constrains were applied and clocks defined.
Should the asynchronous reset/set lines be checked for setup/hold violations?
That corners are usually used for for the STA analysis? Are there exceptions? Why? What's about the typical delays corner? When should it be used?
Thank you!
What steps are usually used for fixing timing violations after first-run synthesis? Let's say that all the boundary constrains were applied and clocks defined.
Should the asynchronous reset/set lines be checked for setup/hold violations?
That corners are usually used for for the STA analysis? Are there exceptions? Why? What's about the typical delays corner? When should it be used?
Thank you!