STA + Functional Simulations -> why needed?

Hi all,

1) Why STA is needed? Don't synthesis tools do the same work?

2) After doing STA, why also some functional vectors should be also run?

Thank you!

good questions

1) Synthesis just transform RTL to gate level netlist. It does not check timing. STA checks timing and tells you the the slowest path in the design which determines the maximum frequency of the design. Note for STA you need synthesized design and synthesis library with timing information. From this, STA tool will determine the slowest path in the design.

2) You need to do post STA simulation to see if STA results are indeed correct. Since STA tool needs constraints which are given to STA tool by humans, it may contain errors. That is why post synthesis simulation is necessary to gain confidence.

Sythesis uses STA to come up with the optimized gate level netlist. There are also many other high level optimization done before optimizing the timing like resource sharing data path optimization.
But if u ask like why we use PT for doing the STA, is because it is a sign off tool which gives u lot of accuracy required at the end not much required at the beginning.

Functional vectors r run for making sure the functionality is not effected.

"Synthesis ... does not check timing" - how so? The synthesis tools are timing aware! Am I missing something?

"STA checks timing and tells you the the slowest path in the design" - cannot the synthesis tools do the same?

"post synthesis simulation is necessary to gain confidence" - what test benches should be run on the Netlist? Should them be the same one as for the RTL verification or some reduced set of them. If not all of them then how to determine which one of them?

Ur right. The synthesis will have a timing engine inside of it to do the timing aware optimizations required.
For example in DC if u type "report timing" it will give u the WC timing path for each domain.
Every stage there requires timing values for optimization both the frontend and backend has timing engine inside of it.


See in sythesis the timing u get is an estimate of the net delays which might be coming from the WLM or other wire load models.
But after routing u have the real net placed physically. So now u have can have the real delay by parasitic extraction which gives u the real RC values by which u run STA and check the final timing.

The PT and DC tool have got the same timing engine (STA) inside of it, except that PT takes more time as u need accuracy more while running the sign off timing.

Hope its clear now...

So, running STA in the pre-layout stage is not necessary? Just to run LEC tools in order to check equity in functionality in RTL and Netlist?
Would u give me a reason why STA is involved in the pre-layout stage?

dmitryl said:

So, running STA in the pre-layout stage is not necessary? Just to run LEC tools in order to check equity in functionality in RTL and Netlist?
Would u give me a reason why STA is involved in the pre-layout stage?

Click to expand...

STA is nothing by calculating the timing of ur design.
It is required at all the stages of the design. Without that how can the tool optimize in all the stages for better timing ????

STA is nothing by calculating the timing of ur design.
It is required at all the stages of the design. Without that how can the tool optimize in all the stages for better timing ????

Click to expand...

I mean why running PT is MUST in the pre-layout stage? You wrote by yourself that DC does the same job even faster!

U dont have to run PT at the earlier stages say at the frontend. It is not required at all.
But if u want to run it, u can run with SDF (standard delay format) file given as input to the PT.
The SDF file will be dumped by the synopsys DC tool.

But in PT u have many other features by which u can analyse the timing deeply but u cant make any changes to the design in PT.

in PT u have many other features by which u can analyze the timing deeply

Click to expand...

What features for example? How PT can help me in timing closure in the pre-layout stage?

Nothing much u can explore in the pre layout stage with PT.
So PT is used in the post layout stage for signing off timing.

Hope now everything is clear....

STA is not must in pre-layout stage, it's used in post layout for timing signoff. STA is static timing check, so we need post simulation for check dynamic timing, such as asyn logic.

Thank you!