Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

component instantiation query in verilog

Status
Not open for further replies.
R

raghava216

Junior Member level 3
Junior Member level 3
Joined
Mar 10, 2011
Messages
27
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,646
I am trying to instantiate a verilog module 'comp' in another.

module comp(a,b);

input [1:0] a;
output b;

// some logic

endmodule


In another module, 'my_module', lets say a, b and c are declared.
'comp' is instantiated as follows:

comp X (.a[0](a),.a[1](b),.b(c));

While compiling, I get an error with the above line of code.
Whats wrong with this?
Any idea?
 
Last edited:

nisshith said:
write comp X (.a({a,b}),.b(c));
Click to expand...

Yes Got it. The inputs need to be concatenated.

But how is the order taken?

In the above example, I want to map a to a[0] and b to a[1].

Which is correct?

comp X (.a({b,a}), .b(c)); OR comp X(.a({a,b}), .b(c));
 
Last edited:

i think comp X(.a({a,b}), .b(c)); will give the desired result. check in the RTL view.
 

nisshith said:
i think comp X(.a({a,b}), .b(c)); will give the desired result. check in the RTL view.
Click to expand...

I wrote "comp X(.a({b,a}), .b(c));" in my code.

I am not able to see to bit level like a[0] is mapped to what and a[1] is mapped to what. But, On placing mouse pointer on the signal a(1:0), it displays "Input pin: a(1:0) => Signal b,a" in RTL view. I am using Xilinx 12.2 ISE.

So, I feel comp X(.a({b,a}), .b(c)); is correct for the case a[0] => a and a[1] => b and
comp X(.a({a,b}), .b(c)); is correct for the case a[0] => b and a[1] => a.
 

it may be correct in your case. actually comp X(.a({b,a}), .b(c)) will give different results in definition "input [1:0] a" and "input [0:1] a", so whatever comes in RTL go with it. I always get confused in this.
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top