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truncating std_logic_vector question

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vivo_m

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I'm trying to multiply two std_logic_vector(7 downto 0), i know the result will be new std_logic_vector(15 downto 0) but actually i want the output result to be std_logic_vector(7 downto 0)..
is there any idea how can i do this..
 

signal temp_result : std_logic_vector ( 15 downto 0 )
signal result : std_logic_vector ( 7 downto 0 ) ;

temp_result <= vector1 * vector2 ;
result <= temp_result ( 7 downto 0 ) ;
 
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    vivo_m

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you cannot multiply std_logic_vectors. you need to use signed or unsigned type. But the method is the same as above.
 

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