Endymion
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I'm writing a simple SPI based shift register in VHDL for a Max V CPLD. I've come up with the following code:
Note the line "tmp <= 10101111" is just for testing. In reality, I will load PI into tmp. I've tested the code and it works well when I utilize Mode 0 SPI (it doesn't work when CPOL = '1' and I change elsif falling_edge(CLK) to elsif rising_edge(CLK)). Would appreciate some advice on this.
But is the above code improvable? Am I falling into some newbie pitfalls of VHDL?
Code:
library ieee;
use ieee.std_logic_1164.all;
entity PISO is
port(CLK, SI, nCS : in std_logic;
outpin: out std_logic;
PI : in std_logic_vector(7 downto 0);
SO : out std_logic);
end PISO;
architecture archi of PISO is
signal tmp: std_logic_vector(PI'high downto PI'low);
signal bitOut: std_logic;
begin
process (CLK,nCS)
begin
if (nCS='1') then
tmp <= "10101111";
elsif falling_edge(CLK) then
tmp <= tmp(PI'high -1 downto PI'low) & '0';
end if;
end process;
SO <= tmp(PI'high) when nCS = '0' else 'Z';
outpin <= '1';
end archi;Note the line "tmp <= 10101111" is just for testing. In reality, I will load PI into tmp. I've tested the code and it works well when I utilize Mode 0 SPI (it doesn't work when CPOL = '1' and I change elsif falling_edge(CLK) to elsif rising_edge(CLK)). Would appreciate some advice on this.
But is the above code improvable? Am I falling into some newbie pitfalls of VHDL?
