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Help on verilog code!

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yann_sun

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Hi, all
Why the commands in "always begin end" executed at the time zero?
The following is the brief codes.

Code: 
...
initial begin 
A <= 0;
# 10 A <= 1;
...
end
...
..
.
always @(negedge A) begin
some commands 
some more
...
end
 

A is not a clock signal, so it is level triggered, not edge triggered.
 

Non-blocking assignment A <= 0; bring delta-cycle, this expression equivalently #0 A=0;
Use A=0; instead A <= 0; for solve this problem.
 

Using A=0 still fails to solve the problem. There is no discrepancy. Any hint?
 

If you are using any simulator that support SystemVerilog, if you write your code as

reg A = 0;

The initialization of A is guaranteed to execute before any always or initial block execute.
Alternatively you could make the first assignment to A=1, but then you would have the problem for @(posedge A) if there are any.
 
Last edited:
Thanks Dave.

Where there is a will, there is a way.
 

that helps
 
Last edited:

because in verilog any signal default is X, intial begin A =0 end will bring A jump from X to 0, that's mean a negedge tigger
 
It means that "reg" gets executed before any other code/block , irrespective of priorities . but why "reg" gets executed first ?
dave_59 said:
If you are using any simulator that support SystemVerilog, if you write your code as

reg A = 0;

The initialization of A is guaranteed to execute before any always or initial block execute.
Alternatively you could make the first assignment to A=1, but then you would have the problem for @(posedge A) if there are any.
Click to expand...
 

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