inout to input ports connections

hi i am vhdl user and i have some problem
i have to modules that has inout ports that i need to connect between them

i mean inout port from the first midule have to connected to the inout port from the secound module.

when i do so with signal i got an error
do u guys have any solution
some buffer or somthing....

your inout port is bidirectional, so you will need to build a mechanism that deals with it.

If you connect the inout to an intermediate signal, you should be able to connect it to the input
BUT you need a tri-state buffer connected to the inout port, otherwise the design wont compile.

TrickyDicky said:

If you connect the inout to an intermediate signal, you should be able to connect it to the input
BUT you need a tri-state buffer connected to the inout port, otherwise the design wont compile.

Click to expand...

What is the major use of having a tristate buffer inside FPGA?. Only it is necessary when you interface with external devices, not internal FFs.Correct me if wrong

I dont think he really means a tristate buffer operation here. He is just trying to connect two structural designs. Can you display the error?.
And wont the tool automatically infer, if inout port is used in top level design?.

xtcx said:

What is the major use of having a tristate buffer inside FPGA?. Only it is necessary when you interface with external devices, not internal FFs.Correct me if wrong

Click to expand...

All FPGA pins have tri-state drivers in them, to allow connection to external devices (because it will save the pin count having an inout bus). But internally connecting inouts is useless. No modern FPGA has internal tri-states, so any detected are just converted to muxes.

Yeah same as I thought. Internal declaration of inouts are instantiated as mux (If you actually use them as mux).good

Can you show your code and error message?

hi all
thanks everybody to look at this thread.
i know taht i need to use FSM to connect 2 bidirectional buses pin to pin, but i try to find out some trick to avoid clock cycle loosing...
ther isno internal tristate buffers as TrickDicky says but if i feed the port with (others => 'z') its behave like tri-state - am i right?
the error i got os that the signal connected to multiple buffer...

what are you thinks guys about using MEALY STATE MACHINE ? it will save me one clock cycle- i mean

i creat state machine that generate enable signal that use ac enable to the inout port ( however inout port require asignal that describe the datadirection)
i mean while write the enable set and whןle reading the enable reset ( write describe input and read describe output direction to the inout port)
the question is if i will i will create MEALY FSM i think that i will save clock cycle.....i will try it...

Please be clear. Are you trying to use the inout port internally or is it to connect to an external device?

if its internally - STOP DOING IT NOW. you should have separate in and out ports.

There is no requirement to use a state machine on an inout, you just handle the data as you need. If you need a state machine then ok. You only need to drive 'z' when opposite end drives its enable signal (which will be an input to this block).

TrickyDicky said:

You only need to drive 'z' when opposite end drives its enable signal (which will be an input to this block).

Click to expand...

First of all...Why would anyone drive the internal inout ports to 'z' (Atleast if you say that for IO ) ?.


I really dont understand why you want bidirectional IO between components(Atleast if you are saying this for top level design)...Are you trying to implement an FSM to handle data between component 1 and component 2?

Can you explain?.

hi TrickyDicky
i need to connect the inout internally and externally - i mean i getting from outside input adress and inout data , in addtion i have some IP'S- that connect to the top level with inout data bus. so i need to connect the global inout data bus two ways - FROM the top level outsid the FPGA and FROM the IPto the top level.
what do you think - may i generate the enable signal of the inout port in the top level (that will control on the inout signal that connect from the IP to the top level) and send this signal to the ip and there it will controll the ip inout....


the way i use to decleare the inout port is
ENTITY xxx IS
PORT(
gdata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
io_en, clk : IN STD_LOGIC;
ldata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)

END XXX;

ARCHITECTURE RTL OF XXXIS
SIGNAL IN_SIG : STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL OUT_SUG: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN
IN_SIG <= ldata;
outp <= b;
END IF;
END PROCESS;
PROCESS (io_en, gdata) -- Behavioral representation
BEGIN -- of tri-states.
IF( io_en = '0') THEN
gdata<= "ZZZZZZZZ";
out_sig<= gdata;
ELSE
gdata<= in_sig;
out_sig <= gdata;
END IF;
END PROCESS;


could you provide cide of your method to decleare it.

Does your IP provide enable signal for that inout port?.

---------- Post added at 17:10 ---------- Previous post was at 17:06 ----------

How many components are you using and how many inouts are you trying to connect to?.
Is it like this?

component IP is
some_sig : inout std_logic_vector(7 downto 0);
end component

component XXX is
gdata : inout std_logic_vector(7 downto 0);
idata : inout std_logic_vector(7 downto 0);
io_en : in std_logic;
clk : std_logic;
end component

xtcx said:

Does your IP provide enable signal for that inout port?.

---------- Post added at 17:10 ---------- Previous post was at 17:06 ----------

How many components are you using and how many inouts are you trying to connect to?.
Is it like this?

component IP is
some_sig : inout std_logic_vector(7 downto 0);
end component

component XXX is
gdata : inout std_logic_vector(7 downto 0);
idata : inout std_logic_vector(7 downto 0);
io_en : in std_logic;
clk : std_logic;
end component

Click to expand...

yes - that exactly what i mean to.
my problem is to connect inouts ports pin to pin...
i mean i can do it butwit 3 lossing clock cycles -o to reco

MMM...so the enable signal you use to connect these two inout pins, takes 3 clks cycles to latch...and is that what you mean?.

xtcx said:

MMM...so the enable signal you use to connect these two inout pins, takes 3 clks cycles to latch...and is that what you mean?.

Click to expand...

yes - that what i mean to.
i am trying to find out a method to latch the data and plotit to/from the gdatainout port with 2 clocks -- look realizable ?

itmr said:

yes - that what i mean to.
i am trying to find out a method to latch the data and plotit to/from the gdatainout port with 2 clocks -- look realizable ?

Click to expand...

First answer me clearly this

Ques 1: How many inouts do you have which maps to pin-outs of the FPGA such as (qdata, idata, etc)?.I mean TOP-LVL ENTITY

Ques 2: How many components (ONLY THE ONES WHICH USE INOUT)are you using under your top-level module (such as IP, xxx, etc)?.

Ques 3: How do you wish to now connect the inouts from top-level to these components. CAN U SHOW SOMETHING LIKE A DIAGRAM\FLOW?.
Eg.,
top <--> Comp1 (IP)
top <--> Comp2 (XXX)

or
Top --> Comp1 (IP)
Top <-- Comp2 (XXX)

or so?...

Got it?

Please give a correct answer to these questions clearly?. Problem is not your English but how you frame words to give technical explanation which is little bit tough for me to get it.

xtcx said:

First answer me clearly this

Ques 1: How many inouts do you have which maps to pin-outs of the FPGA such as (qdata, idata, etc)?.I mean TOP-LVL ENTITY

Ques 2: How many components (ONLY THE ONES WHICH USE INOUT)are you using under your top-level module (such as IP, xxx, etc)?.

Ques 3: How do you wish to now connect the inouts from top-level to these components. CAN U SHOW SOMETHING LIKE A DIAGRAM\FLOW?.
Eg.,
top <--> Comp1 (IP)
top <--> Comp2 (XXX)

or
Top --> Comp1 (IP)
Top <-- Comp2 (XXX)

or so?...

Got it?

Please give a correct answer to these questions clearly?. Problem is not your English but how you frame words to give technical explanation which is little bit tough for me to get it.

Click to expand...

ok i will try better to let you understand me

my fpga have to be connected to DSP.
the busses i have -
gdata ; inout
gaddress ; in
wr_en ; in
rd_en ;in
ackmoledge ; out


I have PLB (peripheral local bus) in the fpga that get the data from the dsp - mux the base adrress to the suitable ip and sending the offset adress and the data to the ip ( in case of reading data the PLB send just offset adress and waiting for data)

so probably i have one main inout port ( from the dsp to the PLB) and another 8 local inout ports ( from the ips) that connected to the PLB.
( my ips are memory,uart controller,spi controller, and i2c controller that connected to another sensors..)

from the PLB to the IPS u have no problem to connect the inout because i generate state machine that know to detect in or out and direct the data accordingly

but when i need to connect the PLB to the FPGA INOUT PORT to the DSP, i have problem to connect in my top level the inout from the PLB to the FPGA INOUT ( i cant connect it with regular signal...). so i need to generate again state machine and to loose 2 clocks....

i hope my problem is understood now .

attached the block diagram of the project ( i put just one ip to demonstrate the project

https://obrazki.elektroda.pl/41_1329123367.jpg

There are clear alternatives to designing the "local bus" as bidirectional inout bus.

As already explained, inout will be translated to FPGA internal multiplexers if there's more than one potential driver connected to the bus. Designing the bus with unidirectional lines and a multilexer to the top level inout port would be the explicite way to describe the intended data flow.

If you prefer "virtual" inouts for the behavioral description, the problem is basically the same as with a multiplexer: There can be only one driver to the bus at a time, so you need to make the tristate enable signals strictly mutual exclusive. In other words, there must be a enumeration-like control signal ALL_OFF, IP1_DRVING, IP2_DRIVING...

It's not absolutely necessary to have a state machine control the bus activation, it could be also asynchronously derived from external address and control signals, if you consider that data output register and tristate enables can be controlled differently. The more critical part is in fact achieving consistent behaviour of the data registers. It may require synchronizing of unrelated bus signals and thus involve inconvenient delays.

All in all, you should more think about the data flow and respective timing details rather than technical details of VHDL syntax like connection of inout ports. If the data flow scheme is clear, the behavioral description will follow easily.

itmr said:

ok i will try better to let you understand me

my fpga have to be connected to DSP.
the busses i have -
gdata ; inout
gaddress ; in
wr_en ; in
rd_en ;in
ackmoledge ; out

Click to expand...

Good explanation. I can understand better now. One more doubt\clarification.
What I understood was that you were trying to build some sort of soft processor like thing. Did you use microblaze in this case?. Since I remember PLBs and some IPs you said looked more like they were from EDK environment.

Okay let that be....no issues.
You said all IPs have inout port, how are they mapped? and what signal is that inout port (an addr or data etc?)?.
If inout of all IPs are addr\data, how are you mapping and sharing same address port for all IP's through PLB bus?. Using an FSM to switch between read\write mode for each componenet?.

Let me speak more in coding style.

1) The gdata which is an inout coming from DSP, will be shared\connected to PLB. But is it also shared to all IPs????. Or the output of PLB(Which is also an inout) is shared to all other IPs?.

from the PLB to the IPS u have no problem to connect the inout because i generate state machine that know to detect in or out and direct the data accordingly

Click to expand...

2) From PLB to all IPs, which inout bus are you sharing?. Same gdata inout from DSP?.Or any other inout port from PLB?. Make sure.
3) How do you connect gdata inout port to PLB?. Just direct portmapping?. Well, if direct port mapping means, the PLB can handle the inout internally...Chk that
4) In Xilinx PLB datasheet, I couldnot find PLB using any inout ports after all. Then how do you connect gdata to PLB bus first?. Are you using any enable? or so..and latching to input and output ports based on that?
can you be more specific here?. this is the place where you are having problems.

xtcx said:

Good explanation. I can understand better now. One more doubt\clarification.
What I understood was that you were trying to build some sort of soft processor like thing. Did you use microblaze in this case?. Since I remember PLBs and some IPs you said looked more like they were from EDK environment.

Okay let that be....no issues.
You said all IPs have inout port, how are they mapped? and what signal is that inout port (an addr or data etc?)?.
If inout of all IPs are addr\data, how are you mapping and sharing same address port for all IP's through PLB bus?. Using an FSM to switch between read\write mode for each componenet?.

Let me speak more in coding style.

1) The gdata which is an inout coming from DSP, will be shared\connected to PLB. But is it also shared to all IPs????. Or the output of PLB(Which is also an inout) is shared to all other IPs?.



2) From PLB to all IPs, which inout bus are you sharing?. Same gdata inout from DSP?.Or any other inout port from PLB?. Make sure.
3) How do you connect gdata inout port to PLB?. Just direct portmapping?. Well, if direct port mapping means, the PLB can handle the inout internally...Chk that
4) In Xilinx PLB datasheet, I couldnot find PLB using any inout ports after all. Then how do you connect gdata to PLB bus first?. Are you using any enable? or so..and latching to input and output ports based on that?
can you be more specific here?. this is the place where you are having problems.

Click to expand...

Probably ita a kind of soft processor but more comfortable for the user...

about Q1 - the PLB connected to the inout port of the DSP and has more 8 INOUT PORTS THAT CONNECTED TO THE IP'S.
the inout from the plb shared with the inout of the ips - ( the plb mux the base address and share the whole data and the offset addres. the adress bus has 24 bits -10 base and 14 offset that usually point to internal ips register.)

about Q2 - the pls share with the ips the same data.

Q3 - i need to use tristate buffer with output enable to connect the gdata from the DSP to PLB - am i right?
Q4 - i used tristate buffer with OE.

am i clear now ? can you find some way to do so right way? do you have any recommendation for me ?