Calculate W/L using gm/Id method for Folded Cascode OTA

Hi...
Can any one help me how to calculate W/L ratio using gm/Id methodology???
any usefull Document for that???


Thanking you....

It tells: gm/Id = 2/Vov (where Vov = Vgs-Vt). The general design procedure sees Vov as the adjustable parameter to achieve the Gain ,BW and Power requirements. But in todays deep nano meter technology, Vov alone is not sufficient. So now you ahve to see gm and Id both to adjust Vgs-Vt. So Increase Gm, but constraint is Id. so adjust W/L to meet your Gm and Id and adjust Vgs -Vt in that.

Thanks for your reply..
But i dont know how i can get W/L using graph of gm/Id and Id/(W/L) curve??


Thanking you....

Its just your design requirement. When you decide Vgs-Vth, You take care Id and Gm also. gm will give you gain, Id will increase your power dissipation. So trade off. What is the gain requirement, so choose gm and then make trade of in Id and W/L. If you got Id then fix the W/L. Higher W/L increases the size and hence capacitance, that reduces the inherent speed of the device.

thank u varunkant2k

i am using 0.18um tech..

my specifications are

Gain = 60 dB
UGF = 500Mhz
CL = 0.1 pf
Vdd = 1.8V

now from where i have to start??
how can i start calculations of W/L??
i have attach my circuit..


thanking u

500MHz , really a tough spec to follow. Anyways, you have selected right architecture. Now burn some good current and adjust gm of first stage and increase cascode resistance by using gain boosting.

thank u

how much current and gm i will have to adjust???
First stage means input differential pair??

See, these are really designing parameters, and one can't speak without knowing many of other requirements. I will suggest you to read the designing of folded cascode and then ask if you get any problem.

div.5200 said:

i am using 0.18um tech..

my specifications are

Gain = 60 dB
UGF = 500Mhz
CL = 0.1 pf
Vdd = 1.8V

now from where i have to start??
how can i start calculations of W/L??

Click to expand...

See David M. Binkley "Tradeoffs and Optimization in Analog CMOS Design"
Chap. 5: Design of CMOS Operational Transconductance Amplifiers Optimized for DC, Balanced, and AC Performance.
Chap. 5.5: DESIGN OPTIMIZATION AND RESULTING PERFORMANCE FOR THE CASCODED OTAS
Chap. 5.5.1.2: AC optimization

You'll find there an optimization procedure for cascoded OTAs incl. MOSFET dimensioning in 0.18µm tech. Even if the highest frequency "ac" example doesn't meet your requirements re. gain & UGF (gain=56dB, UGF≈60MHz, with currents of 100µA) I think you can profit from the method.

from you BW / load cap you can get the input gm required. decide gm/id. that will give you id required. the corresponding Id/(w/l) for given gm/id will get you length and width. the trick to get the right gm/id parameter depending on which device it is. (ie input/cascode/ load)

erikl said:

See David M. Binkley "Tradeoffs and Optimization in Analog CMOS Design"
Chap. 5: Design of CMOS Operational Transconductance Amplifiers Optimized for DC, Balanced, and AC Performance.
Chap. 5.5: DESIGN OPTIMIZATION AND RESULTING PERFORMANCE FOR THE CASCODED OTAS
Chap. 5.5.1.2: AC optimization

You'll find there an optimization procedure for cascoded OTAs incl. MOSFET dimensioning in 0.18µm tech. Even if the highest frequency "ac" example doesn't meet your requirements re. gain & UGF (gain=56dB, UGF≈60MHz, with currents of 100µA) I think you can profit from the method.

Click to expand...

Hi,erikl
I know this book,but the model used is EVK,does it suit for BSIM?

urian said:

... the model used is EVK, does it suit for BSIM?

Click to expand...

Sure, why not?

I think the book promotes a tool that uses EKV internally. I don't know what input format it requires.
I think the general limitations of the approach are different ones: this is about optimizing single devices performance. But in a circuit, devices are connected and their Vgs, Vds, Id, ... depend on each others' W, L. Secondly, circuit performance depends on multiple devices; you cannot optimize power consumption or phase margin just by looking at one device at a time. Third, this is all about DC operating points, but what about transient performances like slew rates or linearity? Fourth, the concept doesn't handle multi-corner optimization well.
All gm-Id based methods I've seen so far require significant effort on the designer's side to develop the equations and optimization procedure manually, for each circuit topology anew. It's not easier than traditional analog design.