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finding registers in RTL or gate level design with associated clock

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tariq786

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Hi guys,

Assume i have RTL OR synthesized gate level netlist of a multi-clock design.So the design has clock domain crossings (CDC).

Is there a way, i can get all the flip flop/Registers in the design and their associated clock?

Any idea?
 

I do not know a straight forward method, but while synthesizing, the tool (DC) would spit out what flops are being synthesized. you can then use this info and write a TCL script to report all the corresponding clocks..
 
i dont have spyglass tool. Suggest any synopsys,cadence or opensource tool
 

Cadence has a CDC tool - Conformal CDC you may want to try that. But if your at synthesis stage a small TCL would be fast.
 
report_fanout -from your clock source through hierarchy to leaf cell.
 
i think this would still not catch all the registers, if you have clock going through some mux select..
all registers which were to get the clock depending on the mux select will not be reported. Pls correct me if wrong
 
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