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VCS simulation error concerning memory (32-bit)

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priyanka24

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hi..
me tried to implement one of my verilog code in synopsys. but in VCS tool itself when me pressed run option to get simulation waveforms it continous to run and after some time got following message:




what should i do to remove this can anyone know??
 

Re: VCS simulation error

A 32 bit version can handle maximum 2^32 bit (4GB) memory. It seems memory requirement during simulation crossed the 4GB limit. To address memory more than 4GB you require a 64 bit version.
 

Re: VCS simulation error

yadavvlsi said:
A 32 bit version can handle maximum 2^32 bit (4GB) memory. It seems memory requirement during simulation crossed the 4GB limit. To address memory more than 4GB you require a 64 bit version.
Click to expand...

but its simple program. so such memory is required for that. so whats the solution in that case?
 

May be some problems exist in your RTL or testbench.
For example, $finish is never achived so it causes "infinite" time to complete simulation).

Code: 
// tb.v

reg a;

// initial block with stimulas
initial begin

a = 1; // forever 1

wait(a == 0); // this event will never occur, but the simulator will wait.... and eat memory I think

$finish;

end
:wink:
 
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